soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header

Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.

TEST=intel/archercity CRB

Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu 2022-07-05 22:31:29 +08:00 committed by Felix Held
parent 3108ba5a07
commit 3d5fd72c0f
4 changed files with 3 additions and 12 deletions

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@ -5,6 +5,9 @@
#include <acpi/acpi.h>
#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
#define MAX_ACPI_MEMORY_AFFINITY_COUNT 256
/**
Select C-state map set in config cstate_states
**/

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@ -55,10 +55,6 @@ are permitted provided that the following conditions are met:
#define MAX_SAD_RULES 24
#define MAX_DRAM_CLUSTERS 1
#define MAX_IMC_PER_SOCKET 2
#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
)
#define MEM_TYPE_RESERVED (1 << 8)
#define MEM_ADDR_64MB_SHIFT_BITS 26

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@ -40,11 +40,7 @@ are permitted provided that the following conditions are met:
}
#define MAX_IMC_PER_SOCKET MAX_IMC
#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
#define MAX_SMB_INSTANCE 2
#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
)
#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
#endif // _HOB_MEMMAP_H_

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@ -41,10 +41,6 @@ are permitted provided that the following conditions are met:
#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
#define MAX_IMC_PER_SOCKET 2
#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8
#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
)
#define MEM_TYPE_RESERVED (1 << 8)
#define MEM_ADDR_64MB_SHIFT_BITS 26