Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -848,7 +848,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat)
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{
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/* Initialize the DQS Positions in preparation for
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* Reciever Enable Training.
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* Receiver Enable Training.
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* Write Position is 1/2 Memclock Delay
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* Read Position is 1/2 Memclock Delay
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*/
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@@ -863,7 +863,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat, u8 Channel)
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{
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/* Initialize the DQS Positions in preparation for
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* Reciever Enable Training.
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* Receiver Enable Training.
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* Write Position is no Delay
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* Read Position is 1/2 Memclock Delay
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*/
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@@ -800,7 +800,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat)
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{
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/* Initialize the DQS Positions in preparation for
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* Reciever Enable Training.
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* Receiver Enable Training.
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* Write Position is 1/2 Memclock Delay
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* Read Position is 1/2 Memclock Delay
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*/
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@@ -814,7 +814,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat, u8 Channel)
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{
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/* Initialize the DQS Positions in preparation for
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* Reciever Enable Training.
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* Receiver Enable Training.
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* Write Position is no Delay
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* Read Position is 1/2 Memclock Delay
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*/
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