mb/system76/adl-p: darp8: Enable AER on CPU PCIe RP

Change-Id: Ia2979038f19e1af536d216b5867db2aeff9558ad
2023-01-03 10:35:49 -07:00
parent d78cc205c2
commit 3dacf7f26b
1 changed files with 1 additions and 1 deletions
--- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
@@ -20,7 +20,7 @@ chip soc/intel/alderlake
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN