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mainboard/google/hatch: Move gpio GPP_C* NC down into baseboard

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The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.

This patch handles the GPP_C15 group for easier review.

BUG=b:142094759
BRANCH=none
TEST=builds

Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Edward O'Callaghan 2019-12-24 15:15:35 +11:00 committed by Edward O'Callaghan
parent c4a3f51618
commit 3dbe593906
9 changed files with 48 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/hatch/variants/akemi/gpio.c
View File

@ -35,8 +35,6 @@ static const struct pad_config ssd_sku_gpio_table[] = {
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
@ -94,8 +92,6 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */

8
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -140,12 +140,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
/* C14 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_C14, 1, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* C16 : PCH_I2C_TRACKPAD_SDA */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* C17 : PCH_I2C_TRACKPAD_SCL */

2
src/mainboard/google/hatch/variants/dratini/gpio.c
View File

@ -29,8 +29,6 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A19, NONE),
/* C12 : FPMCU_PCH_BOOT1 */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */

9
src/mainboard/google/hatch/variants/hatch/gpio.c
View File

@ -32,7 +32,14 @@ static const struct pad_config gpio_table[] = {
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C13 : EC_PCH_INT_L */
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)};
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
};
const struct pad_config *override_gpio_table(size_t *num)
{

2
src/mainboard/google/hatch/variants/helios/gpio.c
View File

@ -43,8 +43,6 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C6, NONE),
/* C7 : GPP_C7 ==> NC */
PAD_NC(GPP_C7, NONE),
/* C15 : UART1_CTS# ==> NC */
PAD_NC(GPP_C15, NONE),
/* C23 : UART2_CTS# ==> NC */
PAD_NC(GPP_C23, NONE),
/* D5 : ISH_I2C0_SDA ==> NC */

6
src/mainboard/google/hatch/variants/jinlon/gpio.c
View File

@ -25,6 +25,12 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C12 : FPMCU_PCH_BOOT1 */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */

18
src/mainboard/google/hatch/variants/kindred/gpio.c
View File

@ -31,6 +31,12 @@ static const struct pad_config ssd_sku_gpio_table[] = {
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
@ -84,6 +90,12 @@ static const struct pad_config emmc_sku_gpio_table[] = {
PAD_NC(GPP_E4, NONE),
/* E5 : SATA_DEVSLP1 ==> NC */
PAD_NC(GPP_E5, NONE),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
@ -131,6 +143,12 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */

9
src/mainboard/google/hatch/variants/mushu/gpio.c
View File

@ -32,7 +32,14 @@ static const struct pad_config gpio_table[] = {
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* C13 : EC_PCH_INT_L */
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)};
PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
};
const struct pad_config *override_gpio_table(size_t *num)
{

6
src/mainboard/google/hatch/variants/stryke/gpio.c
View File

@ -33,6 +33,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C11, NONE),
/* C12 : NC */
PAD_NC(GPP_C12, NONE),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */