oryp10: enable DGPU

Change-Id: I856b221c099d8b52e14d5b5482499e873060491c

src/mainboard/system76/adl-p/variants/oryp10/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x65f5 inherit
 
-		device ref pcie5_0 off
+		device ref pcie5_0 on
 			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
 			register "cpu_pcie_rp[CPU_RP(2)]" = "{
 				.clk_src = 3,

src/mainboard/system76/adl-p/variants/oryp10/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;