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drivers/ipmi to lib: Fix misspellings & capitalization issues

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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2023-09-04 15:37:07 -06:00 committed by Felix Held
parent 3933ed5e5a
commit 3e25f85d68
27 changed files with 43 additions and 43 deletions
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4
src/drivers/maxim/max77686/max77686.h
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@ -77,8 +77,8 @@ enum {
};
enum {
MAX77686_MV = 0, /* mili volt */
MAX77686_UV /* micro volt */
MAX77686_MV = 0, /* millivolt */
MAX77686_UV /* microvolt */
};
/**

2
src/drivers/maxim/max77802/max77802.h
View File

@ -199,7 +199,7 @@ enum {
#define MAX77802_BUCK_TYPE2_ON (1 << 4)
#define MAX77802_BUCK_TYPE2_IGNORE_PWRREQ (1 << 5)
/* LDO35 1.2 volt value for bridge ic */
/* LDO35 1.2 volt value for bridge IC */
#define MAX77802_LDO35CTRL1_1_2V (1 << 4)
#define MAX77802_LOD35CTRL1_ON (1 << 6)

4
src/drivers/mipi/panel-CMN_P097PFG_SSD2858.c
View File

@ -21,7 +21,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
.init = {
PANEL_GENERIC(0xff, 0x00),
/* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2} }, MULT=0x49
* 27 Mhz => 985.5 Mhz */
* 27 MHz => 985.5 MHz */
PANEL_GENERIC(0x00, 0x08, 0x01, 0xf4, 0x01, 0x49),
/* MTXDIV=1, SYSDIV=3 (=> 4) */
PANEL_GENERIC(0x00, 0x0c, 0x00, 0x00, 0x00, 0x03),
@ -34,7 +34,7 @@ struct panel_serializable_data P097PFG_SSD2858 = {
PANEL_GENERIC(0x10, 0x08, 0x01, 0x20, 0x08, 0x45),
PANEL_GENERIC(0x10, 0x1c, 0x00, 0x00, 0x00, 0x00),
PANEL_GENERIC(0x20, 0x0c, 0x00, 0x00, 0x00, 0x04),
/* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */
/* Pixel clock 985.5 MHz * 0x49/0x4b = 959 MHz */
PANEL_GENERIC(0x20, 0x10, 0x00, 0x4b, 0x00, 0x49),
PANEL_GENERIC(0x20, 0xa0, 0x00, 0x00, 0x00, 0x00),
/* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */

2
src/drivers/mrc_cache/mrc_cache.c
View File

@ -431,7 +431,7 @@ static void log_event_cache_update(uint8_t slot, enum result res)
/* During ramstage this code purposefully uses incoherent transactions between
* read and write. The read assumes a memory-mapped boot device that can be used
* to quickly locate and compare the up-to-date data. However, when an update
* is required it uses the writeable region access to perform the update. */
* is required it uses the writable region access to perform the update. */
static void update_mrc_cache_by_type(int type,
struct mrc_metadata *new_md,
const void *new_data,

2
src/drivers/net/atl1e.c
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This driver sets the macaddress of a Atheros AR8121/AR8113/AR8114
* This driver sets the MAC address of an Atheros AR8121/AR8113/AR8114
*/
#include <device/mmio.h>

2
src/drivers/ocp/include/vpd.h
View File

@ -64,7 +64,7 @@ enum cxl_memory_mode {
#define DISABLE_BOOTDRIVE "disable_bootdrive"
#define DISABLE_BOOTDRIVE_DEFAULT 0 /* By default don't disable */
/* Skip Global reset so that information in Previous Boot Error Hob won't be cleared */
/* Skip Global reset so that information in Previous Boot Error HOB won't be cleared */
#define SKIP_GLOBAL_RESET "skip_global_reset"
#define SKIP_GLOBAL_RESET_DEFAULT 1

2
src/drivers/smmstore/store.c
View File

@ -185,7 +185,7 @@ static enum cb_err scan_end(struct region_device *store)
if (k_sz != 0xffffffff) {
printk(BIOS_WARNING,
"eof of data marker looks invalid: 0x%x\n", k_sz);
"EOF of data marker looks invalid: 0x%x\n", k_sz);
return CB_ERR;
}

2
src/drivers/spi/spi-generic.c
View File

@ -101,7 +101,7 @@ unsigned int spi_crop_chunk(const struct spi_slave *slave, unsigned int cmd_len,
/* Subtract command length from usable buffer size. If
deduct_opcode_len is set, only subtract the number command bytes
after the opcode. If the adjusted cmd_len is larger than ctrlr_max
return 0 to inidicate an error. */
return 0 to indicate an error. */
if (deduct_cmd_len) {
if (ctrlr_max >= cmd_len) {
ctrlr_max -= cmd_len;

2
src/drivers/spi/spi_flash_internal.h
View File

@ -112,7 +112,7 @@ extern const struct spi_flash_vendor_info spi_flash_atmel_vi;
extern const struct spi_flash_vendor_info spi_flash_eon_vi;
extern const struct spi_flash_vendor_info spi_flash_gigadevice_vi;
extern const struct spi_flash_vendor_info spi_flash_macronix_vi;
/* Probing order matters between the spansion sequence. */
/* Probing order matters between the Spansion sequence. */
extern const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi;
extern const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi;
extern const struct spi_flash_vendor_info spi_flash_spansion_vi;

14
src/drivers/spi/spi_sdcard.c
View File

@ -207,7 +207,7 @@ static int response_resolve(int response_type, uint8_t *response,
{
__maybe_unused static const char * const sd_err[] = {
"Card is locked",
"wp erase skip | lock/unlok cmd failed",
"wp erase skip | lock/unlock cmd failed",
"error",
"CC error",
"card err failed",
@ -302,7 +302,7 @@ static int spi_sdcard_do_command_help(const struct spi_sdcard *card,
/* send crc */
spi_sdcard_sendbyte(card, crc);
/* waitting for response */
/* waiting for response */
wait = 0xffff;
while (((c = spi_sdcard_recvbyte(card)) & 0x80) && --wait)
;
@ -318,7 +318,7 @@ static int spi_sdcard_do_command_help(const struct spi_sdcard *card,
}
if (type == RSP_R1b) {
/* waitting done */
/* waiting done */
wait = 0xffffff;
while (c == 0 && --wait)
c = spi_sdcard_recvbyte(card);
@ -368,7 +368,7 @@ size_t spi_sdcard_size(const struct spi_sdcard *card)
/* enable CS */
spi_sdcard_enable_cs(card);
/* waitting start block token */
/* waiting start block token */
wait = 0xffff;
while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait)
;
@ -505,7 +505,7 @@ int spi_sdcard_single_read(const struct spi_sdcard *card,
/* enable cs */
spi_sdcard_enable_cs(card);
/* waitting start block token */
/* waiting start block token */
wait = 0xffff;
while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait)
;
@ -558,7 +558,7 @@ int spi_sdcard_multiple_read(const struct spi_sdcard *card,
for (int i = 0; i < block_num; i++) {
uint16_t c = 0;
/* waitting start block token */
/* waiting start block token */
wait = 0xffff;
while ((spi_sdcard_recvbyte(card) != CT_BLOCK_START) && --wait)
;
@ -662,7 +662,7 @@ int spi_sdcard_single_write(const struct spi_sdcard *card,
if (spi_sdcard_do_command(card, WRITE_BLOCK, block_address, NULL))
return -1;
/* eanbele cs */
/* enable cs */
spi_sdcard_enable_cs(card);
/* send start block token */

8
src/drivers/spi/tpm/tpm.c
View File

@ -2,7 +2,7 @@
/* This is a driver for a SPI interfaced TPM2 device.
*
* It assumes that the required SPI interface has been initialized before the
* driver is started. A 'sruct spi_slave' pointer passed at initialization is
* driver is started. A 'struct spi_slave' pointer passed at initialization is
* used to direct traffic to the correct SPI interface. This driver does not
* provide a way to instantiate multiple TPM devices. Also, to keep things
* simple, the driver unconditionally uses of TPM locality zero.
@ -134,7 +134,7 @@ static enum cb_err start_transaction(int read_write, size_t bytes, unsigned int
* flow control (Section "6.4.5 Flow Control").
*
* Again, the slave (TPM device) expects each transaction to start
* with a 4 byte header trasmitted by master. The header indicates if
* with a 4 byte header transmitted by master. The header indicates if
* the master needs to read or write a register, and the register
* address.
*
@ -231,7 +231,7 @@ static void trace_dump(const char *prefix, uint32_t reg,
/*
* Data read from or written to FIFO or not in 4 byte
* quantiites is printed byte at a time.
* quantities is printed byte at a time.
*/
for (i = 0; i < bytes; i++) {
if (current_char &&
@ -697,7 +697,7 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
if (debug_level_)
printk(BIOS_DEBUG, "\n");
/* Verify that 'data available' is not asseretd any more. */
/* Verify that 'data available' is not asserted any more. */
read_tpm_sts(&status);
if ((status & expected_status_bits) != TPM_STS_VALID) {
printk(BIOS_ERR, "unexpected final status %#x\n", status);

4
src/drivers/spi/tpm/tpm.h
View File

@ -11,7 +11,7 @@
#define TPM_LOCALITY_0_SPI_BASE 0x00d40000
/*
* A tpm device descriptor, values read from the appropriate device regisrers
* A TPM device descriptor, values read from the appropriate device registers
* are cached here.
*/
struct tpm2_info {
@ -33,7 +33,7 @@ tpm_result_t tpm2_init(struct spi_slave *spi_if);
* Each command processing consists of sending the command to the TPM, by
* writing it into the FIFO register, then polling the status register until
* the TPM is ready to respond, then reading the response from the FIFO
* regitster. The size of the response can be gleaned from the 6 byte header.
* register. The size of the response can be gleaned from the 6 byte header.
*
* This function places the response into the tpm2_response buffer and returns
* the size of the response.

2
src/drivers/tpm/ppi.c
View File

@ -647,7 +647,7 @@ void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
/*
* Returns One if the PPI spec supports this functions.
* That doesn't necessarily mean that the firmware implemtents it, or the
* That doesn't necessarily mean that the firmware implements it, or the
* TPM can execute the function.
*
* Arg0: Integer PPI function

4
src/drivers/wifi/generic/acpi.c
View File

@ -471,7 +471,7 @@ static void emit_sar_acpi_structures(const struct device *dev, struct dsm_profil
if (dev->path.type == DEVICE_PATH_PCI && dev->vendor != PCI_VID_INTEL)
return;
/* Retrieve the sar limits data */
/* Retrieve the SAR limits data */
if (get_wifi_sar_limits(&sar_limits) < 0) {
printk(BIOS_ERR, "failed getting SAR limits!\n");
return;
@ -549,7 +549,7 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *sco
struct dsm_profile dsm = {0};
uint8_t dsm_count = 0;
/* Fill Wifi sar related ACPI structures */
/* Fill Wifi SAR related ACPI structures */
if (CONFIG(USE_SAR)) {
emit_sar_acpi_structures(dev, &dsm);

2
src/ec/lenovo/h8/h8.c
View File

@ -53,7 +53,7 @@ enum battery {
/* h8 charge priority. Defines if primary or secondary
* battery is charged first.
* Because NVRAM is complete the otherway around as this register,
* Because NVRAM is complete the other way around as this register,
* it's inverted by if
*/
static void h8_charge_priority(enum battery battery)

4
src/include/acpi/acpi.h
View File

@ -1727,8 +1727,8 @@ void acpi_create_slit(acpi_slit_t *slit,
/*
* Create a Memory Proximity Domain Attributes structure for HMAT,
* given proximity domain for the attached initiaor, and
* proximimity domain for the memory.
* given proximity domain for the attached initiator, and
* proximity domain for the memory.
*/
int acpi_create_hmat_mpda(acpi_hmat_mpda_t *mpda, u32 initiator, u32 memory);
/* Create Heterogeneous Memory Attribute Table */

2
src/include/boot_device.h
View File

@ -63,7 +63,7 @@ int boot_device_wp_region(const struct region_device *rd,
void boot_device_init(void);
/*
* Restrict read/write access to the bootmedia using platform defined rules.
* Restrict read/write access to the boot-media using platform defined rules.
*/
#if CONFIG(BOOTMEDIA_LOCK_NONE) || (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE) && ENV_RAMSTAGE)
static inline void boot_device_security_lockdown(void) {}

2
src/include/bootstate.h
View File

@ -51,7 +51,7 @@
* |
* BS_OS_RESUME_CHECK -------- BS_OS_RESUME
* | |
* BS_WRITE_TABLES os handoff
* BS_WRITE_TABLES OS handoff
* |
* BS_PAYLOAD_LOAD
* |

2
src/include/cpu/x86/mp.h
View File

@ -75,7 +75,7 @@ struct mp_ops {
uintptr_t staggered_smbase);
/*
* Optionally provide a callback that is called after the APs
* and the BSP have gone through the initialion sequence.
* and the BSP have gone through the initialization sequence.
*/
void (*post_mp_init)(void);
};

2
src/include/device/device.h
View File

@ -229,7 +229,7 @@ void mp_init_cpus(DEVTREE_CONST struct bus *cpu_bus);
static inline void mp_cpu_bus_init(struct device *dev)
{
/*
* When no LAPIC device is specified in the devietree inside the CPU cluster device,
* When no LAPIC device is specified in the devicetree inside the CPU cluster device,
* neither a LAPIC device nor the link/bus between the CPU cluster and the LAPIC device
* will be present in the static device tree and the link_list struct element of the
* CPU cluster device will be NULL. In this case add one link, so that the

2
src/include/device/dram/ddr2.h
View File

@ -92,7 +92,7 @@ struct dimm_attr_ddr2_st {
u8 rev;
/* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */
u8 cas_supported;
/* Maximum cloclk to data cycle times for various CAS.
/* Maximum clock to data cycle times for various CAS.
* Fields 0 and 1 are unused. */
u32 cycle_time[8];
/* Maximum data access times for various CAS.

2
src/include/device/pci_def.h
View File

@ -24,7 +24,7 @@
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */
/* Support User Definable Features [obsolete] */
#define PCI_STATUS_UDF 0x40
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */

2
src/include/input-event-codes.h
View File

@ -755,7 +755,7 @@
#define KEY_MACRO_PRESET3 0x2b5
/*
* Some keyboards have a buildin LCD panel where the contents are controlled
* Some keyboards have a built-in LCD panel where the contents are controlled
* by the host. Often these have a number of keys directly below the LCD
* intended for controlling a menu shown on the LCD. These keys often don't
* have any labeling so we just name them KEY_KBD_LCD_MENU#

4
src/include/nhlt.h
View File

@ -27,7 +27,7 @@ struct nhlt_format_config;
* Most code should use the SoC variants of the functions because
* there is required logic needed to be performed by the SoC. The SoC
* code should be abstracting the inner details of these functions that
* specically apply to NHLT objects for that SoC.
* specifically apply to NHLT objects for that SoC.
*
* An example sequence:
*
@ -146,7 +146,7 @@ uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr);
* Serialize NHLT object to ACPI table. Take in the beginning address of where
* the table will reside oem_id and oem_table_id and return the address of the
* next ACPI table. On error 0 will be returned. The NHLT object is no longer
* valid after thisfunction is called.
* valid after this function is called.
*/
uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr,
const char *oem_id, const char *oem_table_id,

2
src/include/rmodule.h
View File

@ -16,7 +16,7 @@ enum {
struct rmodule;
/* Public API for loading rmdoules. */
/* Public API for loading rmodules. */
int rmodule_parse(void *ptr, struct rmodule *m);
void *rmodule_parameters(const struct rmodule *m);
void *rmodule_entry(const struct rmodule *m);

2
src/lib/ramdetect.c
View File

@ -18,7 +18,7 @@ int __weak probe_mb(const uintptr_t dram_start, const uintptr_t size)
void *ptr = (void *) addr;
size_t i;
/* Don't accidentally clober oneself. */
/* Don't accidentally clobber oneself. */
if (OVERLAP(addr, addr + sizeof(uint32_t), (uintptr_t)_program, (uintptr_t) _eprogram))
return 1;

4
src/lib/smbios.c
View File

@ -216,7 +216,7 @@ static const char *memory_device_type(u8 code)
if (code >= MEMORY_TYPE_OTHER && code <= MEMORY_TYPE_HBM3)
return type[code - 1];
return "Unsupproted";
return "Unsupported";
}
static void dump_smbios_type17(struct dimm_info *dimm)
@ -646,7 +646,7 @@ int smbios_write_type9(unsigned long *current, int *handle,
t->slot_designation = smbios_add_string(t->eos, name ? name : "SLOT");
t->slot_type = type;
/* TODO add slot_id supoort, will be "_SUN" for ACPI devices */
/* TODO add slot_id support, will be "_SUN" for ACPI devices */
t->slot_id = id;
t->slot_data_bus_width = bandwidth;
t->current_usage = usage;