superio/ite/it8659e: Add driver for ITE IT8659E
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2 (For H Version)". TEST=Initialize IT8659E on the new Protectli platform Change-Id: I11657ec6e1c880f0cee247071486a904a92bb7a1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michał Żygowski
Nico Huber
parent
e80b4c7f1a
commit
3f56bd2394
@ -14,6 +14,7 @@ subdirs-y += it8528e
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subdirs-y += it8613e
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subdirs-y += it8623e
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subdirs-y += it8629e
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subdirs-y += it8659e
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subdirs-y += it8712f
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subdirs-y += it8718f
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subdirs-y += it8720f
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10
src/superio/ite/it8659e/Kconfig
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10
src/superio/ite/it8659e/Kconfig
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config SUPERIO_ITE_IT8659E
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bool
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select SUPERIO_ITE_COMMON_PRE_RAM
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select SUPERIO_ITE_ENV_CTRL
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select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
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select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
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select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
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select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN
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3
src/superio/ite/it8659e/Makefile.mk
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3
src/superio/ite/it8659e/Makefile.mk
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# SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-$(CONFIG_SUPERIO_ITE_IT8659E) += superio.c
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219
src/superio/ite/it8659e/acpi/superio.asl
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219
src/superio/ite/it8659e/acpi/superio.asl
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the IT8659E SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x1 UARTA Implemented, tested
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* 0x2 UARTB Implemented, tested
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* 0x4 EC Implemented, tested
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* 0x5 KBC Implemented, untested
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* 0x6 MOUSE Implemented, untested
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* 0x7 GPIO Implemented, tested
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* 0xa CIR Not implemented
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* IT8659E_SHOW_UARTA If defined, UARTA will be exposed.
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* IT8659E_SHOW_UARTB If defined, UARTB will be exposed.
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* IT8659E_SHOW_KBC If defined, the KBC will be exposed.
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* IT8659E_SHOW_PS2M If defined, PS/2 mouse support will be exposed.
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* IT8659E_SHOW_EC If defined, the EC will be exposed.
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* IT8659E_SHOW_GPIO If defined, the GPIO will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME IT8659E
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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#define CONFIGURE_CONTROL CCTL
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Device (SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("ITE IT8659E Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* Mutex for accesses to the configuration ports */
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Mutex (CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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CONFIGURE_CONTROL, 8, /* Global configure control */
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used i/o ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x01
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#define PNP_ENTER_MAGIC_3RD 0x55
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#if SUPERIO_PNP_BASE == 0x2e
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#define PNP_ENTER_MAGIC_4TH 0x55
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#else
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#define PNP_ENTER_MAGIC_4TH 0xaa
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#endif
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#define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
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#define PNP_EXIT_SPECIAL_VAL 0x02
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#include <superio/acpi/pnp_config.asl>
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#ifdef IT8659E_SHOW_UARTA
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_PNP_NO_DIS
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 1
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8659E_SHOW_UARTB
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_PNP_NO_DIS
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8659E_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#undef SUPERIO_PNP_NO_DIS
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#define SUPERIO_KBC_LDN 5
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#ifdef IT8659E_SHOW_PS2M
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#define SUPERIO_KBC_PS2LDN 6
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#endif
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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/*
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* Generic setup for EC device.
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*
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* IT8659E_EC_IO0 The alignment and length of the first PnP i/o
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* IT8659E_EC_IO1 The alignment and length of the second PnP i/o
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* IT8659E_EC_IRQ0 If defined, the first PnP IRQ register is enabled
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*/
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#ifdef IT8659E_SHOW_EC
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_NO_DIS
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 4
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#define SUPERIO_PNP_DDN "ITE IT8659E Environmental Controller"
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#ifdef IT8659E_EC_IO0
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#endif
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#ifdef IT8659E_EC_IO1
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#define SUPERIO_PNP_IO1 0x08, 0x04
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#endif
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#ifdef IT8659E_EC_IRQ0
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#define SUPERIO_PNP_IRQ0
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#endif
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#include <superio/acpi/pnp_generic.asl>
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#endif
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/*
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* Generic setup for GPIO device.
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*
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* IT8659E_EC_IO0 The alignment and length of the first PnP i/o
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* IT8659E_EC_IO1 The alignment and length of the second PnP i/o
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* resource (comma separated, e.g. `0x02, 0x08`,
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* optional)
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* IT8659E_EC_IRQ0 If defined, the first PnP IRQ register is enabled
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*/
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#ifdef IT8659E_SHOW_GPIO
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_NO_DIS
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 7
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#define SUPERIO_PNP_DDN "ITE IT8659E GPIO"
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#define SUPERIO_PNP_NO_DIS
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#ifdef IT8659E_GPIO_IO0
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#define SUPERIO_PNP_IO0 0x04, 0x04
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#endif
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#ifdef IT8659E_GPIO_IO1
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#define SUPERIO_PNP_IO1 0x01, 0x08
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#endif
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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12
src/superio/ite/it8659e/chip.h
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12
src/superio/ite/it8659e/chip.h
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef SUPERIO_ITE_IT8659E_CHIP_H
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#define SUPERIO_ITE_IT8659E_CHIP_H
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#include <superio/ite/common/env_ctrl_chip.h>
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struct superio_ite_it8659e_config {
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struct ite_ec_config ec;
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};
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#endif /* SUPERIO_ITE_IT8659E_CHIP_H */
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34
src/superio/ite/it8659e/it8659e.h
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34
src/superio/ite/it8659e/it8659e.h
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@ -0,0 +1,34 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef SUPERIO_ITE_IT8659E_H
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#define SUPERIO_ITE_IT8659E_H
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#define IT8659E_SP1 0x01 /* Com1 */
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#define IT8659E_SP2 0x02 /* Com2 */
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#define IT8659E_EC 0x04 /* Environment controller */
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#define IT8659E_KBCK 0x05 /* PS/2 keyboard */
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#define IT8659E_KBCM 0x06 /* PS/2 mouse */
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#define IT8659E_GPIO 0x07 /* GPIO */
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#define IT8659E_CIR 0x0A /* CIR */
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/* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */
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#define GPIO_REG_POLARITY(x) (0xb0 + (x))
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#define GPIO_POL_NO_INVERT 0
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#define GPIO_POL_INVERT 1
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/* GPIO Internal Pull-up: 1: Enable, 0: Disable */
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#define GPIO_REG_PULLUP(x) (0xb8 + (x))
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#define GPIO_PULLUP_DIS 0
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#define GPIO_PULLUP_EN 1
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/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */
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#define GPIO_REG_ENABLE(x) (0xc0 + (x))
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#define GPIO_ALT_FN 0
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#define GPIO_SIMPLE_IO 1
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/* GPIO Mode: 0: input mode, 1: output mode */
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#define GPIO_REG_OUTPUT(x) (0xc8 + (x))
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#define GPIO_INPUT_MODE 0
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#define GPIO_OUTPUT_MODE 1
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#endif /* SUPERIO_ITE_IT8659E_H */
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66
src/superio/ite/it8659e/superio.c
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66
src/superio/ite/it8659e/superio.c
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/device.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <superio/conf_mode.h>
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#include <superio/ite/common/env_ctrl.h>
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#include "chip.h"
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#include "it8659e.h"
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static void it8659e_init(struct device *dev)
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{
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const struct superio_ite_it8659e_config *conf = dev->chip_info;
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const struct resource *res;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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case IT8659E_EC:
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res = probe_resource(dev, PNP_IDX_IO0);
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if (!conf || !res)
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break;
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ite_ec_init(res->base, &conf->ec);
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break;
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case IT8659E_KBCK:
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pc_keyboard_init(NO_AUX_DEVICE);
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break;
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default:
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = it8659e_init,
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.ops_pnp_mode = &pnp_conf_mode_870155_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, IT8659E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, 0x0ff8, },
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{ NULL, IT8659E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2, 0x0ff8, },
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{ NULL, IT8659E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
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PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB |
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PNP_MSCD, 0x0ff0, 0x0ff0, },
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{ NULL, IT8659E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, 0x0fff, 0x0fff, },
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{ NULL, IT8659E_KBCM, PNP_IRQ0 | PNP_MSC0, },
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{ NULL, IT8659E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
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PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
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PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, 0x0ff8, 0x0ff8, },
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{ NULL, IT8659E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_ite_it8659e_ops = {
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.name = "ITE IT8659E Super I/O",
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.enable_dev = enable_dev,
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};
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