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sb/intel/i82801jx: Add function to detect s3 resume

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File copied from i82801gx.

Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans 2017-04-12 00:10:38 +02:00 committed by Martin Roth
parent e5dcaf1269
commit 41114650d0
3 changed files with 56 additions and 0 deletions
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1
src/southbridge/intel/i82801jx/Makefile.inc
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@ -37,5 +37,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_smbus.c
romstage-y += early_lpc.c
endif

54
src/southbridge/intel/i82801jx/early_lpc.c Normal file
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@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <timestamp.h>
#include <cpu/x86/tsc.h>
#include <console/console.h>
#include <arch/acpi.h>
#include "i82801jx.h"
uint64_t get_initial_timestamp(void)
{
tsc_t base_time = {
.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
};
return tsc_to_uint64(base_time);
}
int southbridge_detect_s3_resume(void)
{
u32 reg32;
/* Read PM1_CNT */
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
if (!acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
} else {
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
/* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
return 1;
}
}
return 0;
}

1
src/southbridge/intel/i82801jx/i82801jx.h
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@ -226,6 +226,7 @@ int smbus_read_byte(unsigned device, unsigned address);
void i82801jx_early_init(void);
void i82801jx_dmi_setup(void);
void i82801jx_dmi_poll_vc1(void);
int southbridge_detect_s3_resume(void);
#endif
#endif