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gaze18 and oryp11: Fix CPU root port definitions

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Change-Id: I1d1834786b08f2b8ba00642477dd26d9d1201e0f
This commit is contained in:
Jeremy Soller
2023-02-22 12:40:46 -07:00
parent 3fbec1478d
commit 41b92819f3
2 changed files with 6 additions and 6 deletions
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6
src/mainboard/system76/rpl/variants/gaze18/overridetree.cb
View File

@ -20,15 +20,15 @@ chip soc/intel/alderlake
device ref pcie5_0 on device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 3 (GPU) # CPU PCIe RP#2 x8, Clock 3 (GPU)
register "pch_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3, .clk_src = 3,
.clk_req = 3, .clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
}" }"
end end
device ref pcie4_0 on device ref pcie4_0 on
# PCIE PEG0 x4, Clock 0 (SSD0) # CPU RP#1 x4, Clock 0 (SSD0)
register "pch_pcie_rp[CPU_RP(1)]" = "{ register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0, .clk_src = 0,
.clk_req = 0, .clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,

6
src/mainboard/system76/rpl/variants/oryp11/overridetree.cb
View File

@ -20,7 +20,7 @@ chip soc/intel/alderlake
device ref pcie5_0 on device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 3 (GPU) # CPU PCIe RP#2 x8, Clock 3 (GPU)
register "pch_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3, .clk_src = 3,
.clk_req = 3, .clk_req = 3,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
@ -28,7 +28,7 @@ chip soc/intel/alderlake
end end
device ref pcie4_0 on device ref pcie4_0 on
# CPU RP#1 x4, Clock 0 (SSD2) # CPU RP#1 x4, Clock 0 (SSD2)
register "pch_pcie_rp[CPU_RP(1)]" = "{ register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0, .clk_src = 0,
.clk_req = 0, .clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,
@ -36,7 +36,7 @@ chip soc/intel/alderlake
end end
device ref pcie4_1 on device ref pcie4_1 on
# PCIE RP#3 x4, Clock 4 (SSD1) # PCIE RP#3 x4, Clock 4 (SSD1)
register "pch_pcie_rp[CPU_RP(3)]" = "{ register "cpu_pcie_rp[CPU_RP(3)]" = "{
.clk_src = 4, .clk_src = 4,
.clk_req = 4, .clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER, .flags = PCIE_RP_LTR | PCIE_RP_AER,