soc/intel/{apl,cnl,jsl}: Enable EISA HID support for DPTF
This patch selects `HAVE_DPTF_EISA_HID` config for APL, CNL and JSL platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice01c5720ba7f15861899d89981225cb76f9fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71109 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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@@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
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select GENERIC_GPIO_LIB
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select HAVE_ASAN_IN_ROMSTAGE
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select HAVE_CF9_RESET_PREPARE
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select HAVE_DPTF_EISA_HID
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select HAVE_INTEL_FSP_REPO if !SOC_INTEL_GEMINILAKE
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@@ -65,6 +65,7 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_M_XIP
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select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
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select GENERIC_GPIO_LIB
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select HAVE_DPTF_EISA_HID
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select HAVE_FSP_GOP
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select HAVE_FSP_LOGO_SUPPORT
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select HAVE_HYPERTHREADING
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@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
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select FSP_M_XIP
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select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
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select GENERIC_GPIO_LIB
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select HAVE_DPTF_EISA_HID
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select HAVE_FSP_GOP
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select INTEL_DESCRIPTOR_MODE_CAPABLE
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select HAVE_SMI_HANDLER
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