soc/rockchip: Remove blank lines before '}' and after '{'

Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/rockchip/common/edp.c

@@ -147,7 +147,6 @@ static int rk_edp_aux_enable(struct rk_edp *edp)
 	} while (!stopwatch_expired(&sw));
 
 	return -1;
-
 }
 
 static int rk_edp_is_aux_reply(struct rk_edp *edp)
@@ -213,7 +212,6 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp,
 	while (length) {
 		len = MIN(length, 16);
 		for (try_times = 0; try_times < 10; try_times++) {
-
 			/* Clear AUX CH data buffer */
 			val = BUF_CLR;
 			write32(&edp->regs->buf_data_ctl, val);
@@ -251,7 +249,6 @@ static int rk_edp_dpcd_transfer(struct rk_edp *edp,
 				break;
 			else
 				printk(BIOS_WARNING, "read dpcd Aux Transaction fail!\n");
-
 		}
 
 		if (retval)
@@ -629,7 +626,6 @@ static int rk_edp_hw_link_training(struct rk_edp *edp)
 		return -1;
 	}
 	return 0;
-
 }
 
 static int rk_edp_select_i2c_device(struct rk_edp *edp,

src/soc/rockchip/common/vop.c

@@ -94,7 +94,6 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
 	struct rockchip_vop_regs *preg = vop_regs[vop_id];
 
 	switch (mode) {
-
 	case VOP_MODE_HDMI:
 		clrsetbits32(&preg->sys_ctrl,
 			     M_ALL_OUT_EN, V_HDMI_OUT_EN(1));

src/soc/rockchip/rk3288/clock.c

@@ -304,7 +304,6 @@ void rkclk_init(void)
 	write32(&cru_ptr->cru_mode_con,
 		RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
 		RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM));
-
 }
 
 void rkclk_configure_cpu(enum apll_frequencies apll_freq)
@@ -665,5 +664,4 @@ unsigned int rkclk_i2c_clock_for_bus(unsigned int bus)
 	default:
 		return -1; /* Should never happen. */
 	}
-
 }

src/soc/rockchip/rk3288/sdram.c

@@ -683,7 +683,6 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
 		for (i = 0; i < 4; i++)
 			clrbits32(&ddr_publ_regs->datx8[i].dxgcr,
 				DQSRTT | DQRTT);
-
 	}
 }
 
@@ -798,7 +797,6 @@ static void set_bandwidth_ratio(u32 channel, u32 n)
 			DXDLLCR_DLLSRST);
 	}
 	setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2);
-
 }
 
 static int data_training(u32 channel,
@@ -1074,7 +1072,6 @@ size_t sdram_size_mb(void)
 	u32 ch;
 
 	if (!size_mb) {
-
 		u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]);
 		u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);