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mb/google/brask/variants/moli: correct USB3 port2 tx_de_emp

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Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for
IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX
failed.

BUG=b:236661824
TEST=emerge-brask coreboot and check USB3 port2 RX pass

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raihow Shi
2022-07-14 16:26:07 +08:00
committed by Martin L Roth
parent 50eef6566b
commit 44bc4cd5d4
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/brya/variants/moli/overridetree.cb
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@@ -26,6 +26,12 @@ chip soc/intel/alderlake
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2 Port3
register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # Enable USB2 Port4
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port9
register "usb3_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A2
register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3
register "tcc_offset" = "0" # TCC of 100C
device domain 0 on