haswell: Relocate mainboard_romstage_entry
to northbridge
This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
@@ -1,11 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/pei_data.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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@@ -21,9 +21,9 @@ void mainboard_config_rcba(void)
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RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -70,5 +70,5 @@ void mainboard_romstage_entry(void)
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},
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};
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -1,11 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <device/pnp_ops.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/pei_data.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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@@ -21,9 +21,9 @@ void mainboard_config_rcba(void)
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RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -70,5 +70,5 @@ void mainboard_romstage_entry(void)
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},
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};
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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@@ -43,9 +42,9 @@ void mainboard_config_rcba(void)
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RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -100,6 +99,5 @@ void mainboard_romstage_entry(void)
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},
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};
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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@@ -43,9 +42,9 @@ void mainboard_config_rcba(void)
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RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -73,8 +72,7 @@ void mainboard_romstage_entry(void)
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.usb_xhci_on_resume = 1,
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};
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variant_romstage_entry(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&pei_data);
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variant_romstage_entry(pei_data);
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}
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@@ -2,7 +2,6 @@
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#include <stdint.h>
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#include <stddef.h>
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/raminit.h>
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@@ -45,9 +44,9 @@ void mainboard_config_rcba(void)
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RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -112,6 +111,5 @@ void mainboard_romstage_entry(void)
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},
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};
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -1,10 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <stdint.h>
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#include <arch/romstage.h>
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#include <cpu/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/pei_data.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <option.h>
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@@ -43,9 +43,9 @@ void mb_late_romstage_setup(void)
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}
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -92,5 +92,5 @@ void mainboard_romstage_entry(void)
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},
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};
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -1,9 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/intel/haswell/haswell.h>
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#include <arch/romstage.h>
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/pei_data.h>
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#include <northbridge/intel/haswell/raminit.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <stdint.h>
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@@ -20,9 +20,9 @@ void mainboard_config_rcba(void)
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RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
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}
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void mainboard_romstage_entry(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data = {
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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@@ -68,5 +68,5 @@ void mainboard_romstage_entry(void)
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},
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};
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romstage_common(&pei_data);
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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}
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@@ -189,8 +189,6 @@
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void intel_northbridge_haswell_finalize_smm(void);
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struct pei_data;
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void romstage_common(struct pei_data *pei_data);
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void mb_late_romstage_setup(void); /* optional */
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void haswell_early_initialization(void);
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@@ -8,6 +8,9 @@
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/* Optional function to copy SPD data for on-board memory */
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void copy_spd(struct pei_data *peid);
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/* Necessary function to initialize pei_data with mainboard-specific settings */
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void mainboard_fill_pei_data(struct pei_data *pei_data);
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void sdram_initialize(struct pei_data *pei_data);
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void setup_sdram_meminfo(struct pei_data *pei_data);
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int fixup_haswell_errata(void);
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@@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <console/console.h>
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#include <cf9_reset.h>
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#include <timestamp.h>
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@@ -22,10 +23,16 @@ void __weak mb_late_romstage_setup(void)
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{
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}
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void romstage_common(struct pei_data *pei_data)
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/* The romstage entry point for this platform is not mainboard-specific, hence the name */
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void mainboard_romstage_entry(void)
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{
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int wake_from_s3;
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struct pei_data pei_data = {
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};
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mainboard_fill_pei_data(&pei_data);
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enable_lapic();
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wake_from_s3 = early_pch_init();
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@@ -52,15 +59,15 @@ void romstage_common(struct pei_data *pei_data)
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post_code(0x3a);
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/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
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pei_data->boot_mode = wake_from_s3 ? 2 : 0;
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pei_data.boot_mode = wake_from_s3 ? 2 : 0;
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timestamp_add_now(TS_BEFORE_INITRAM);
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report_platform_info();
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copy_spd(pei_data);
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copy_spd(&pei_data);
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sdram_initialize(pei_data);
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sdram_initialize(&pei_data);
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timestamp_add_now(TS_AFTER_INITRAM);
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@@ -71,7 +78,7 @@ void romstage_common(struct pei_data *pei_data)
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if (!wake_from_s3) {
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cbmem_initialize_empty();
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/* Save data returned from MRC on non-S3 resumes. */
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save_mrc_data(pei_data);
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save_mrc_data(&pei_data);
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} else if (cbmem_initialize()) {
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#if CONFIG(HAVE_ACPI_RESUME)
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/* Failed S3 resume, reset to come up cleanly */
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@@ -81,7 +88,7 @@ void romstage_common(struct pei_data *pei_data)
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haswell_unhide_peg();
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setup_sdram_meminfo(pei_data);
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setup_sdram_meminfo(&pei_data);
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romstage_handoff_init(wake_from_s3);
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