mb/google/brya/var/trulo: Add Thermal descriptions
This patch adds Thermal related entries (like, TDP, TCC and enabling DPTF config with required sensor configuration) to the devicetree. BUG=b:351976770 TEST=Builds successfully for google/trulo. Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Subrata Banik
parent
76723874a7
commit
46caf3e37d
@ -1,4 +1,8 @@
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fw_config
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field THERMAL_SOLUTION 0 0
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option THERMAL_SOLUTION_6W 0
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option THERMAL_SOLUTION_15W 1
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end
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field STORAGE 30 31
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option STORAGE_EMMC 0
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option STORAGE_NVME 1
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@ -6,6 +10,7 @@ fw_config
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option STORAGE_UNKNOWN 3
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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@ -16,6 +21,11 @@ chip soc/intel/alderlake
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# S0ix enable
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register "s0ix_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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register "tcc_offset" = "10" # TCC of 90
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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@ -154,8 +164,222 @@ chip soc/intel/alderlake
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},
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}"
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register "power_limits_config[ADL_N_041_6W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 25,
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.tdp_pl4 = 78,
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}"
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register "power_limits_config[ADL_N_081_7W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 25,
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.tdp_pl4 = 78,
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}"
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register "power_limits_config[ADL_N_081_15W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 35,
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.tdp_pl4 = 83,
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}"
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device domain 0 on
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device ref igpu on end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DDR""
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register "options.tsr[1].desc" = ""charger""
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register "options.tsr[2].desc" = ""ambient""
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(70, 100),
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TEMP_PCT(60, 65),
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TEMP_PCT(42, 60),
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TEMP_PCT(39, 55),
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TEMP_PCT(38, 50),
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TEMP_PCT(35, 43),
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TEMP_PCT(31, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(60, 100),
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TEMP_PCT(55, 65),
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TEMP_PCT(52, 60),
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TEMP_PCT(50, 55),
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TEMP_PCT(48, 50),
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TEMP_PCT(45, 43),
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TEMP_PCT(41, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 6000,
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.max_power = 20000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 28 * MSECS_PER_SEC,
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.granularity = 500
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},
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.pl2 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 32 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 500
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 100, 6000, 220, 2200, },
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[1] = { 92, 5500, 180, 1800, },
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[2] = { 85, 5000, 145, 1450, },
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[3] = { 70, 4400, 115, 1150, },
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[4] = { 56, 3900, 90, 900, },
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[5] = { 45, 3300, 55, 550, },
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[6] = { 38, 3000, 30, 300, },
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[7] = { 33, 2900, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 on
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probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
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end
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end
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DDR""
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register "options.tsr[1].desc" = ""charger""
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register "options.tsr[2].desc" = ""ambient""
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(70, 100),
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TEMP_PCT(60, 65),
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TEMP_PCT(42, 58),
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TEMP_PCT(39, 53),
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TEMP_PCT(38, 47),
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TEMP_PCT(35, 43),
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TEMP_PCT(31, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(60, 100),
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TEMP_PCT(55, 65),
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TEMP_PCT(52, 58),
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TEMP_PCT(50, 53),
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TEMP_PCT(48, 47),
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TEMP_PCT(45, 43),
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TEMP_PCT(41, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 15000,
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.max_power = 20000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 28 * MSECS_PER_SEC,
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.granularity = 500
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},
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.pl2 = {
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.min_power = 35000,
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.max_power = 35000,
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.time_window_min = 32 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 500
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 100, 6000, 220, 2200, },
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[1] = { 92, 5500, 180, 1800, },
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[2] = { 85, 5000, 145, 1450, },
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[3] = { 70, 4400, 115, 1150, },
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[4] = { 56, 3900, 90, 900, },
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[5] = { 45, 3300, 55, 550, },
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[6] = { 38, 3000, 30, 300, },
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[7] = { 33, 2900, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 1 on
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probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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