sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/x86/smm: Define single smm_subregion()

Browse Source 
At the moment we only have two splitting of TSEG,
one with and one without IED. They can all use
same implementation.

Make configuration problems of TSEG region assertion
failures.

Rename file from stage_cache.c to tseg_region.c to
reflect it's purpose.

Change-Id: I9daf0dec8fbaaa1f4e6004ea034869f43412d7d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34776
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-05 12:49:09 +03:00
parent b1af16a424
commit 4913d8aed0
11 changed files with 95 additions and 339 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/soc/intel/apollolake/memmap.c
View File

@@ -48,32 +48,3 @@ void smm_region(uintptr_t *start, size_t *size)
*start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}
int smm_subregion(int sub, uintptr_t *start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
smm_region(&sub_base, &sub_size);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
*start = 0;
*size = 0;
return -1;
}
*start = sub_base;
*size = sub_size;
return 0;
}