soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs
PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating programming for ADL_N FSP. Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Subrata Banik
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491afc3cc7
@@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
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}
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s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
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#if CONFIG(FSP_TYPE_IOT)
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#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
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/*
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* Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
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* The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1
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