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soc/intel/alderlake: Guard PchPcieClockGating & PchPciePowerGating UPDs

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PchPcieClockGating & PchPciePowerGating UPDs are not available for ADL_N
FSP headers. Add guard to Avoid PchPcieClockGating & PchPciePowerGating
programming for ADL_N FSP.

Change-Id: I2f1625038896b07c354498fe431cad97fb9b5bdb
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82917
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Ronak Kanabar
2024-06-06 12:14:39 +05:30
committed by Subrata Banik
parent bfb39806c9
commit 491afc3cc7
1 changed files with 1 additions and 1 deletions
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src/soc/intel/alderlake/fsp_params.c
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@@ -932,7 +932,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
}
s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
#if CONFIG(FSP_TYPE_IOT)
#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/*
* Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected.
* The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1