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arch/x86: fix cmos post logging in non romcc bootblock

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cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.

BUG=chrome-os-partner:61546

Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18043
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
2017-01-05 10:07:19 -06:00
parent 7ad4dc5e99
commit 49342cd688
3 changed files with 32 additions and 26 deletions
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29
src/include/pc80/mc146818rtc.h
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@@ -221,10 +221,39 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
#define CMOS_POST_EXTRA_DEV_PATH 0x01
void cmos_post_log(void);
/* cmos_post_init() is exposed in this manner because it also needs to be called
* by bootblock code compiled by romcc. */
static inline void cmos_post_init(void)
{
u8 magic = CMOS_POST_BANK_0_MAGIC;
/* Switch to the other bank */
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_1_MAGIC:
break;
case CMOS_POST_BANK_0_MAGIC:
magic = CMOS_POST_BANK_1_MAGIC;
break;
default:
/* Initialize to zero */
cmos_write(0, CMOS_POST_BANK_0_OFFSET);
cmos_write(0, CMOS_POST_BANK_1_OFFSET);
#if CONFIG_CMOS_POST_EXTRA
cmos_write32(CMOS_POST_BANK_0_EXTRA, 0);
cmos_write32(CMOS_POST_BANK_1_EXTRA, 0);
#endif
}
cmos_write(magic, CMOS_POST_BANK_OFFSET);
}
#else
static inline void cmos_post_log(void) {}
static inline void cmos_post_init(void) {}
#endif /* CONFIG_CMOS_POST */
#else /* !CONFIG_ARCH_X86 */
static inline void cmos_post_init(void) {}
#endif /* CONFIG_ARCH_X86 */
#endif /* PC80_MC146818RTC_H */