sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/amd: Add common definition of AMD ACPI MMIO address

Browse Source 
The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code.  Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.

Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson
2017-01-04 14:26:26 -06:00
parent d502dc092a
commit 7ad4dc5e99
11 changed files with 48 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/advansus/a785e-i/mainboard.c
View File

@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@ void enable_int_gfx(void)
/* make sure the Acpi MMIO(fed80000) is accessible */
// XXX Redo this RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

3
src/mainboard/amd/bettong/boardid.c
View File

@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <southbridge/amd/common/amd_defs.h>
#include <boardid.h>
/**
@@ -34,7 +35,7 @@ uint8_t board_id(void)
u8 boardrev = 0;
char boardid;
gpiommioaddr = (void *)0xfed80000ul + 0x1500;
gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500;
value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */
boardrev = value & 1;
value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */

5
src/mainboard/amd/bimini_fam10/mainboard.c
View File

@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/sb800/sb800.h>
@@ -45,12 +46,12 @@ void enable_int_gfx(void)
byte |= 1;
pm_iowrite(0x24, byte);
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

5
src/mainboard/amd/lamar/romstage.c
View File

@@ -30,6 +30,7 @@
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
@@ -59,8 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0x24, 0xCD6);
outb(0x01, 0xCD7);
*(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
*(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
*(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
hudson_lpc_port80();

4
src/mainboard/asus/f2a85-m/romstage.c
View File

@@ -29,6 +29,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
@@ -38,8 +39,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)

5
src/mainboard/asus/m5a88-v/mainboard.c
View File

@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@ void enable_int_gfx(void)
/* make sure the MMIO(fed80000) is accessible */
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

5
src/mainboard/avalue/eax-785e/mainboard.c
View File

@@ -19,6 +19,7 @@
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <southbridge/amd/common/amd_defs.h>
#include <device/pci_def.h>
u8 is_dev3_present(void);
@@ -34,12 +35,12 @@ void enable_int_gfx(void)
/* make sure the Acpi MMIO(fed80000) is accessible */
// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0xD00; /* IoMux Register */
*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
*(gpio_reg + 170) = 0x1; /* gpio_gate */
gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
gpio_reg = (volatile u8 *)AMD_SB_ACPI_MMIO_ADDR + 0x100; /* GPIO Registers */
*(gpio_reg + 0x6) = 0x8;
*(gpio_reg + 170) = 0x0;

4
src/mainboard/biostar/am1ml/romstage.c
View File

@@ -30,6 +30,7 @@
#include <northbridge/amd/agesa/agesawrapper.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <cpu/amd/agesa/s3_resume.h>
#include "cbmem.h"
@@ -44,8 +45,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
static void it_sio_write(pnp_devfn_t dev, u8 reg, u8 value)

4
src/mainboard/msi/ms7721/romstage.c
View File

@@ -30,6 +30,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
@@ -41,8 +42,7 @@
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SUPERIO_ADDRESS 0x4e

22
src/southbridge/amd/common/amd_defs.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Raptor Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _AMD_SB_DEFS_H_
#define _AMD_SB_DEFS_H_
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul
#endif

5
src/southbridge/amd/sb800/early_setup.c
View File

@@ -19,6 +19,7 @@
#include <reset.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <southbridge/amd/common/amd_defs.h>
#include <cbmem.h>
#include "sb800.h"
#include "smbus.c"
@@ -107,8 +108,8 @@ void sb800_clk_output_48Mhz(void)
reg8 &= ~(1 << 1);
pmio_write(0x24, reg8);
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
*(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR+0xE00+0x40) |= 1 << 1; /* 48Mhz */
}
/***************************************
* Legacy devices are mapped to LPC space.