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soc/intel/xeon_sp/spr: Enable 512 MMCONF buses by default

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As of now coreboot only supported one PCI segment group and thus the
MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the
default FSP doesn't allow to disable unused IIO stacks a patched
version had to be used. Those unused IIO stacks consume lots of PCI
bus ranges, leaving no free buses for the secondary side behind PCI
bridges. The IIO disable mechanism doesn't work after ACPI G3 exit
and thus requires multiple reboots when the previous state was G3.

Since coreboot now supports multi PCI segment groups enable 512
MMCONF buses on 4S platforms by default and drop the IIO stack
disable UPDs on ibm/sbp1. This allows to boot faster without the
need for a patched FSP.

The use of multiple PCI segment groups might prevent legacy software
from working properly, however the only board where multiple PCI
segment groups are used uses u-root as default payload.

TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups.
TEST=intel/archercity CRB

Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph
2024-03-13 16:43:09 +01:00
parent 8061957cc1
commit 49fe84e2c2
3 changed files with 30 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/mainboard/ibm/sbp1/romstage.c
View File

@@ -270,8 +270,6 @@ static const UINT8 sbp1_socket_config_iou[CONFIG_MAX_SOCKET][5] = {
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
UINT32 *sktbmp;
/* Set Rank Margin Tool to disable. */
mupd->FspmConfig.EnableRMT = 0x0;
@@ -287,25 +285,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
else
mupd->FspmConfig.serialDebugMsgLvl = 0;
/* Force 256MiB MMCONF (Segment0) only */
mupd->FspmConfig.mmCfgSize = 0x2;
mupd->FspmConfig.PcieHotPlugEnable = 1;
/*
* Disable unused IIO stack:
* Socket 0 : IIO1, IIO4
* Socket 1 : IIO1, IIO2
* Socket 2 : IIO1, IIO5
* Socket 3 : IIO1, IIO5
* Stack Disable bit mapping is:
* IIO stack number: 1 2 3 4 5
* Stack Disable Bit: 1 5 3 2 4
*/
sktbmp = (UINT32 *)&mupd->FspmConfig.StackDisableBitMap[0];
sktbmp[0] = BIT(1) | BIT(2);
sktbmp[1] = BIT(1) | BIT(5);
sktbmp[2] = BIT(1) | BIT(4);
sktbmp[3] = BIT(1) | BIT(4);
soc_config_iio(mupd, sbp1_socket_config, sbp1_socket_config_iou);
}

1
src/soc/intel/xeon_sp/Kconfig
View File

@@ -89,6 +89,7 @@ config ECAM_MMCONF_BASE_ADDRESS
default 0x80000000
config ECAM_MMCONF_BUS_NUMBER
default 512 if MAX_SOCKET = 4
default 256
config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION

29
src/soc/intel/xeon_sp/spr/romstage.c
View File

@@ -211,6 +211,35 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->mmiohBase = 0x2000;
m_cfg->mmiohSize = 0x3;
/*
* By default FSP will set MMCFG size to 256 buses on 1S and 2S platforms
* and 512 buses on 4S platforms. 512 buses are implemented by using multiple
* PCI segment groups and is likely incompatible with legacy software stacks.
*/
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 2048:
m_cfg->mmCfgSize = 5;
break;
case 1024:
m_cfg->mmCfgSize = 4;
break;
case 512:
m_cfg->mmCfgSize = 3;
break;
case 256:
m_cfg->mmCfgSize = 2;
break;
case 128:
m_cfg->mmCfgSize = 1;
break;
case 64:
m_cfg->mmCfgSize = 0;
break;
default:
printk(BIOS_ERR, "%s: Unsupported ECAM_MMCONF_BUS_NUMBER = %d\n",
__func__, CONFIG_ECAM_MMCONF_BUS_NUMBER);
}
m_cfg->BoardTypeBitmask = 0x11111133;
/*