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soc/intel/skylake/chip.h: Reorder declarations

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Place `tdp_pl2_override` above the FSP options as it's not an FSP option.

Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber 2017-05-09 16:14:36 +02:00 committed by Stefan Reinauer
parent 503965f939
commit 4a47e4b8ee
1 changed files with 3 additions and 2 deletions
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src/soc/intel/skylake/chip.h
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@ -94,6 +94,9 @@ struct soc_intel_skylake_config {
/* TCC activation offset */
int tcc_offset;
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
/*
* The following fields come from FspUpdVpd.h.
* These are configuration values that are passed to FSP during
@ -392,8 +395,6 @@ struct soc_intel_skylake_config {
* Setting to 0 (default) disables Heci1 and hides the device from OS
*/
u8 HeciEnabled;
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
u8 PmTimerDisabled;
/* Intel Speed Shift Technology */
u8 speed_shift_enable;