soc/intel/icelake: Rename pch_init()
function
There's two instances of the same function, one for the bootblock and another for romstage. Prefix them with the stage they are executed in. Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -24,5 +24,5 @@ void bootblock_soc_early_init(void)
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void bootblock_soc_init(void)
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{
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report_platform_info();
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pch_init();
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bootblock_pch_init();
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}
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@@ -109,7 +109,7 @@ void pch_early_iorange_init(void)
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pch_enable_lpc();
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}
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void pch_init(void)
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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@@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
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void bootblock_pch_early_init(void);
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/* Bootblock post console init programming */
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void pch_init(void);
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void bootblock_pch_init(void);
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void pch_early_iorange_init(void);
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void report_platform_info(void);
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@@ -7,7 +7,7 @@
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void systemagent_early_init(void);
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void pch_init(void);
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void romstage_pch_init(void);
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/* Board type */
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enum board_type {
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@@ -4,7 +4,7 @@
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#include <intelblocks/tco.h>
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#include <soc/romstage.h>
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void pch_init(void)
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void romstage_pch_init(void)
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{
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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@@ -111,7 +111,7 @@ void mainboard_romstage_entry(void)
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program PCH init */
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pch_init();
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romstage_pch_init();
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/* initialize Heci interface */
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heci_init(HECI1_BASE_ADDRESS);
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