vc/amd/opensil/genoa_poc/mpio: move PCIe port function below mpio chip
Move the gpp_bridge_* device functions that are bridges to the external PCIe ports below the corresponding mpio chip. This avoids the need for dummy devices and does things in a slightly more coreboot-native way. TEST=PCIe lane config reported by openSIL is identical Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
@@ -55,36 +55,30 @@ chip soc/amd/genoa_poc
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device domain 0 on
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device ref iommu_0 on end
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device ref rcec_0 on end
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device ref gpp_bridge_0_0_a on
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chip vendorcode/amd/opensil/genoa_poc/mpio # P2
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "48"
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register "end_lane" = "63"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end # dummy for configuring mpio
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # P2
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "48"
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register "end_lane" = "63"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_0_0_a on end
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end
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device ref gpp_bridge_0_0_b on
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chip vendorcode/amd/opensil/genoa_poc/mpio # G2
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "112"
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register "end_lane" = "127"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "hotplug" = "ServerExpress"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # G2
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "112"
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register "end_lane" = "127"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "hotplug" = "ServerExpress"
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device ref gpp_bridge_0_0_b on end
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end
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device ref gpp_bridge_0_0_c on
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "128"
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register "end_lane" = "131"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "128"
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register "end_lane" = "131"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_0_0_c on end
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end
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device ref gpp_bridge_0_a on
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device ref xhci_0 on end
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@@ -99,51 +93,43 @@ chip soc/amd/genoa_poc
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device domain 1 on
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device ref iommu_1 on end
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device ref rcec_1 on end
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device ref gpp_bridge_1_0_a on
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chip vendorcode/amd/opensil/genoa_poc/mpio # P3
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "16"
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register "end_lane" = "31"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # P3
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "16"
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register "end_lane" = "31"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_1_0_a on end
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end
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device ref gpp_bridge_1_0_b on
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chip vendorcode/amd/opensil/genoa_poc/mpio # G3
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "80"
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register "end_lane" = "95"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # G3
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "80"
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register "end_lane" = "95"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_1_0_b on end
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end
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end
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device domain 2 on
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device ref iommu_2 on end
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device ref rcec_2 on end
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device ref gpp_bridge_2_0_a on
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chip vendorcode/amd/opensil/genoa_poc/mpio # P1
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "32"
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register "end_lane" = "47"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "hotplug" = "ServerExpress"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # P1
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "32"
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register "end_lane" = "47"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "hotplug" = "ServerExpress"
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device ref gpp_bridge_2_0_a on end
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end
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device ref gpp_bridge_2_0_b on
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chip vendorcode/amd/opensil/genoa_poc/mpio # G1
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "64"
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register "end_lane" = "79"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # G1
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "64"
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register "end_lane" = "79"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_2_0_b on end
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end
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end
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@@ -151,56 +137,46 @@ chip soc/amd/genoa_poc
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device domain 3 on
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device ref iommu_3 on end
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device ref rcec_3 on end
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device ref gpp_bridge_3_0_a on
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chip vendorcode/amd/opensil/genoa_poc/mpio # P0
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "0"
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register "end_lane" = "15"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # P0
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "0"
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register "end_lane" = "15"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_3_0_a on end
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end
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device ref gpp_bridge_3_0_b on
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chip vendorcode/amd/opensil/genoa_poc/mpio # G0
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "96"
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register "end_lane" = "111"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio # G0
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "96"
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register "end_lane" = "111"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_3_0_b on end
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end
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device ref gpp_bridge_3_0_c on # WAFL
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "132"
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register "end_lane" = "133"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "132"
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register "end_lane" = "133"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_3_0_c on end # WAFL
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end
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device ref gpp_bridge_3_1_c on # BMC
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "134"
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register "end_lane" = "134"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "bmc" = "1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "134"
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register "end_lane" = "134"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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register "bmc" = "1"
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device ref gpp_bridge_3_1_c on end # BMC
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end
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device ref gpp_bridge_3_2_c on # BMC
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "135"
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register "end_lane" = "135"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device generic 0 on end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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register "type" = "IFTYPE_PCIE"
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register "start_lane" = "135"
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register "end_lane" = "135"
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register "gpio_group" = "1"
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register "aspm" = "L1"
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device ref gpp_bridge_3_2_c on end # BMC
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end
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device ref gpp_bridge_3_a on
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device ref xhci_3 on end
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@@ -16,36 +16,80 @@ chip soc/amd/genoa_poc
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device pci 00.3 alias rcec_0 off end
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device pci 01.0 on end # Dummy device function, do not disable
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device pci 01.1 alias gpp_bridge_0_0_a off end
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device pci 01.2 alias gpp_bridge_0_1_a off end
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device pci 01.3 alias gpp_bridge_0_2_a off end
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device pci 01.4 alias gpp_bridge_0_3_a off end
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device pci 01.5 alias gpp_bridge_0_4_a off end
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device pci 01.6 alias gpp_bridge_0_5_a off end
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device pci 01.7 alias gpp_bridge_0_6_a off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.1 alias gpp_bridge_0_0_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.2 alias gpp_bridge_0_1_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.3 alias gpp_bridge_0_2_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.4 alias gpp_bridge_0_3_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.5 alias gpp_bridge_0_4_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.6 alias gpp_bridge_0_5_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.7 alias gpp_bridge_0_6_a off end
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end
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device pci 02.0 on end # Dummy device function, do not disable
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device pci 02.1 alias gpp_bridge_0_7_a off end
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device pci 02.2 alias gpp_bridge_0_8_a off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 02.1 alias gpp_bridge_0_7_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 02.2 alias gpp_bridge_0_8_a off end
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end
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device pci 03.0 on end # Dummy device function, do not disable
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device pci 03.1 alias gpp_bridge_0_0_b off end
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device pci 03.2 alias gpp_bridge_0_1_b off end
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device pci 03.3 alias gpp_bridge_0_2_b off end
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device pci 03.4 alias gpp_bridge_0_3_b off end
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device pci 03.5 alias gpp_bridge_0_4_b off end
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device pci 03.6 alias gpp_bridge_0_5_b off end
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device pci 03.7 alias gpp_bridge_0_6_b off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.1 alias gpp_bridge_0_0_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.2 alias gpp_bridge_0_1_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.3 alias gpp_bridge_0_2_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.4 alias gpp_bridge_0_3_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.5 alias gpp_bridge_0_4_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.6 alias gpp_bridge_0_5_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 03.7 alias gpp_bridge_0_6_b off end
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end
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device pci 04.0 on end # Dummy device function, do not disable
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device pci 04.1 alias gpp_bridge_0_7_b off end
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device pci 04.2 alias gpp_bridge_0_8_b off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 04.1 alias gpp_bridge_0_7_b off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 04.2 alias gpp_bridge_0_8_b off end
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end
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device pci 05.0 on end # Dummy device function, do not disable
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device pci 05.1 alias gpp_bridge_0_0_c off end
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device pci 05.2 alias gpp_bridge_0_1_c off end
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device pci 05.3 alias gpp_bridge_0_2_c off end
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device pci 05.4 alias gpp_bridge_0_3_c off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 05.1 alias gpp_bridge_0_0_c off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 05.2 alias gpp_bridge_0_1_c off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 05.3 alias gpp_bridge_0_2_c off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 05.4 alias gpp_bridge_0_3_c off end
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end
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device pci 07.0 on end # Dummy device function, do not disable
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device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
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@@ -84,30 +128,66 @@ chip soc/amd/genoa_poc
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device pci 00.3 alias rcec_1 off end
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device pci 01.0 on end # Dummy device function, do not disable
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device pci 01.1 alias gpp_bridge_1_0_a off end
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device pci 01.2 alias gpp_bridge_1_1_a off end
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device pci 01.3 alias gpp_bridge_1_2_a off end
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device pci 01.4 alias gpp_bridge_1_3_a off end
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device pci 01.5 alias gpp_bridge_1_4_a off end
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device pci 01.6 alias gpp_bridge_1_5_a off end
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device pci 01.7 alias gpp_bridge_1_6_a off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.1 alias gpp_bridge_1_0_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.2 alias gpp_bridge_1_1_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.3 alias gpp_bridge_1_2_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.4 alias gpp_bridge_1_3_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.5 alias gpp_bridge_1_4_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.6 alias gpp_bridge_1_5_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 01.7 alias gpp_bridge_1_6_a off end
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end
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device pci 02.0 on end # Dummy device function, do not disable
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device pci 02.1 alias gpp_bridge_1_7_a off end
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device pci 02.2 alias gpp_bridge_1_8_a off end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 02.1 alias gpp_bridge_1_7_a off end
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end
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chip vendorcode/amd/opensil/genoa_poc/mpio
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device pci 02.2 alias gpp_bridge_1_8_a off end
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end
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device pci 03.0 on end # Dummy device function, do not disable
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device pci 03.1 alias gpp_bridge_1_0_b off end
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device pci 03.2 alias gpp_bridge_1_1_b off end
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device pci 03.3 alias gpp_bridge_1_2_b off end
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device pci 03.4 alias gpp_bridge_1_3_b off end
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device pci 03.5 alias gpp_bridge_1_4_b off end
|
||||
device pci 03.6 alias gpp_bridge_1_5_b off end
|
||||
device pci 03.7 alias gpp_bridge_1_6_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.1 alias gpp_bridge_1_0_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.2 alias gpp_bridge_1_1_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.3 alias gpp_bridge_1_2_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.4 alias gpp_bridge_1_3_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.5 alias gpp_bridge_1_4_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.6 alias gpp_bridge_1_5_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.7 alias gpp_bridge_1_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
device pci 04.1 alias gpp_bridge_1_7_b off end
|
||||
device pci 04.2 alias gpp_bridge_1_8_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.1 alias gpp_bridge_1_7_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.2 alias gpp_bridge_1_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
|
||||
@@ -127,30 +207,66 @@ chip soc/amd/genoa_poc
|
||||
device pci 00.3 alias rcec_2 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
device pci 01.1 alias gpp_bridge_2_0_a off end
|
||||
device pci 01.2 alias gpp_bridge_2_1_a off end
|
||||
device pci 01.3 alias gpp_bridge_2_2_a off end
|
||||
device pci 01.4 alias gpp_bridge_2_3_a off end
|
||||
device pci 01.5 alias gpp_bridge_2_4_a off end
|
||||
device pci 01.6 alias gpp_bridge_2_5_a off end
|
||||
device pci 01.7 alias gpp_bridge_2_6_a off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.1 alias gpp_bridge_2_0_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.2 alias gpp_bridge_2_1_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.3 alias gpp_bridge_2_2_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.4 alias gpp_bridge_2_3_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.5 alias gpp_bridge_2_4_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.6 alias gpp_bridge_2_5_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.7 alias gpp_bridge_2_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
device pci 02.1 alias gpp_bridge_2_7_a off end
|
||||
device pci 02.2 alias gpp_bridge_2_8_a off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 02.1 alias gpp_bridge_2_7_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 02.2 alias gpp_bridge_2_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
device pci 03.1 alias gpp_bridge_2_0_b off end
|
||||
device pci 03.2 alias gpp_bridge_2_1_b off end
|
||||
device pci 03.3 alias gpp_bridge_2_2_b off end
|
||||
device pci 03.4 alias gpp_bridge_2_3_b off end
|
||||
device pci 03.5 alias gpp_bridge_2_4_b off end
|
||||
device pci 03.6 alias gpp_bridge_2_5_b off end
|
||||
device pci 03.7 alias gpp_bridge_2_6_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.1 alias gpp_bridge_2_0_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.2 alias gpp_bridge_2_1_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.3 alias gpp_bridge_2_2_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.4 alias gpp_bridge_2_3_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.5 alias gpp_bridge_2_4_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.6 alias gpp_bridge_2_5_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.7 alias gpp_bridge_2_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
device pci 04.1 alias gpp_bridge_2_7_b off end
|
||||
device pci 04.2 alias gpp_bridge_2_8_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.1 alias gpp_bridge_2_7_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.2 alias gpp_bridge_2_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
|
||||
@@ -170,36 +286,80 @@ chip soc/amd/genoa_poc
|
||||
device pci 00.3 alias rcec_3 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
device pci 01.1 alias gpp_bridge_3_0_a off end
|
||||
device pci 01.2 alias gpp_bridge_3_1_a off end
|
||||
device pci 01.3 alias gpp_bridge_3_2_a off end
|
||||
device pci 01.4 alias gpp_bridge_3_3_a off end
|
||||
device pci 01.5 alias gpp_bridge_3_4_a off end
|
||||
device pci 01.6 alias gpp_bridge_3_5_a off end
|
||||
device pci 01.7 alias gpp_bridge_3_6_a off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.1 alias gpp_bridge_3_0_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.2 alias gpp_bridge_3_1_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.3 alias gpp_bridge_3_2_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.4 alias gpp_bridge_3_3_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.5 alias gpp_bridge_3_4_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.6 alias gpp_bridge_3_5_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 01.7 alias gpp_bridge_3_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
device pci 02.1 alias gpp_bridge_3_7_a off end
|
||||
device pci 02.2 alias gpp_bridge_3_8_a off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 02.1 alias gpp_bridge_3_7_a off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 02.2 alias gpp_bridge_3_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
device pci 03.1 alias gpp_bridge_3_0_b off end
|
||||
device pci 03.2 alias gpp_bridge_3_1_b off end
|
||||
device pci 03.3 alias gpp_bridge_3_2_b off end
|
||||
device pci 03.4 alias gpp_bridge_3_3_b off end
|
||||
device pci 03.5 alias gpp_bridge_3_4_b off end
|
||||
device pci 03.6 alias gpp_bridge_3_5_b off end
|
||||
device pci 03.7 alias gpp_bridge_3_6_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.1 alias gpp_bridge_3_0_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.2 alias gpp_bridge_3_1_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.3 alias gpp_bridge_3_2_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.4 alias gpp_bridge_3_3_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.5 alias gpp_bridge_3_4_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.6 alias gpp_bridge_3_5_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 03.7 alias gpp_bridge_3_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
device pci 04.1 alias gpp_bridge_3_7_b off end
|
||||
device pci 04.2 alias gpp_bridge_3_8_b off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.1 alias gpp_bridge_3_7_b off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 04.2 alias gpp_bridge_3_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
device pci 05.1 alias gpp_bridge_3_0_c off end
|
||||
device pci 05.2 alias gpp_bridge_3_1_c off end
|
||||
device pci 05.3 alias gpp_bridge_3_2_c off end
|
||||
device pci 05.4 alias gpp_bridge_3_3_c off end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 05.1 alias gpp_bridge_3_0_c off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 05.2 alias gpp_bridge_3_1_c off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 05.3 alias gpp_bridge_3_2_c off end
|
||||
end
|
||||
chip vendorcode/amd/opensil/genoa_poc/mpio
|
||||
device pci 05.4 alias gpp_bridge_3_3_c off end
|
||||
end
|
||||
|
||||
device pci 07.0 on end # Dummy device function, do not disable
|
||||
device pci 07.1 alias gpp_bridge_3_a off
|
||||
|
||||
@@ -198,5 +198,5 @@ void configure_mpio(void)
|
||||
for (struct device *dev = &dev_root; dev; dev = dev->next)
|
||||
if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops &&
|
||||
dev->chip_info != dev->upstream->dev->chip_info)
|
||||
per_device_config(mpio_data, dev->upstream->dev, dev->chip_info);
|
||||
per_device_config(mpio_data, dev, dev->chip_info);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user