soc/mediatek: Remove blank lines before '}' and after '{'
Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Elyes Haouas
Yu-Ping Wu
parent
e6893677c1
commit
4b76273ac9
@ -46,7 +46,6 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size)
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void color_start(u32 width, u32 height)
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{
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write32(&disp_color0->width, width);
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write32(&disp_color0->height, height);
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write32(&disp_color0->cfg_main, COLOR_BYPASS_ALL | COLOR_SEQ_SEL);
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@ -81,7 +81,6 @@ int mtk_display_init(void)
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return -1;
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}
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} else {
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struct panel_serializable_data *mipi_data = NULL;
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if (panel->get_edid) {
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@ -324,7 +324,6 @@ void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value)
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void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value)
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{
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mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff);
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}
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void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value)
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@ -472,7 +472,6 @@ int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
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base_step_cnt = step_cnt;
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if (best_mul == opt_div + clock_div_constraint)
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break;
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}
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if (!success)
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@ -388,7 +388,6 @@ static void msdc_set_ios(struct sd_mmc_ctrlr *ctrlr)
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msdc_set_clock(host, ctrlr->request_hz);
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msdc_set_buswidth(host, ctrlr->bus_width);
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}
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static void msdc_update_pointers(struct msdc_ctrlr *host)
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@ -111,7 +111,6 @@ static void mtk_uart_init(void)
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write8(&uart_ptr->fcr,
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UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
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UART8250_FCR_CLEAR_XMIT);
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}
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static void mtk_uart_tx_byte(unsigned char data)
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@ -47,7 +47,6 @@ static void da9212_hw_init(uint8_t i2c_num, unsigned char variant_id)
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if (ret)
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printk(BIOS_ERR, "%s failed\n", __func__);
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}
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void da9212_probe(uint8_t i2c_num)
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@ -154,7 +154,6 @@ static void mem_pll_init_phase_sync(u32 channel)
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static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs)
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{
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switch (mempll->phase) {
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case MEMPLL_INIT:
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/* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */
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clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs],
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@ -189,7 +188,6 @@ static void pll_phase_check(u32 channel, struct mem_pll *mempll, int idx)
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(idx + 2), mempll->phase, one_count, zero_count);
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switch (mempll->phase) {
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case MEMPLL_INIT:
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if ((one_count - zero_count) > JMETER_COUNT_N) {
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/* REF lag FBK */
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@ -243,7 +241,6 @@ static void mem_pll_phase_cali(u32 channel)
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JMETER_COUNT << JMETER_COUNTER_SHIFT);
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while (1) {
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for (i = 0; i < 3; i++) {
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if (!mempll[i].done) {
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pll_phase_adjust(channel, &mempll[i], (i + 2) * 3);
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@ -317,7 +314,6 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params)
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udelay(100);
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for (channel = 0; channel < CHANNEL_NUM; channel++) {
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/* mempll_bias_en */
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write32(&ch[channel].ddrphy_regs->mempll[3], 0xd << 28 |
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0x1 << 6);
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@ -751,7 +751,6 @@ void tx_delay_for_wrleveling(u32 channel,
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max_taps = MAX_DQDLY_TAPS - 1;
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for (i = 0; i < DATA_WIDTH_32BIT; i++) {
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index = i / DQS_BIT_NUMBER;
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if (i % DQS_BIT_NUMBER == 0)
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@ -823,7 +822,6 @@ static void set_tx_dly_factor(u32 channel, u32 curr_val, u8 type)
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value += (curr_val << (4 * i));
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switch (type) {
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case TX_DQS:
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write32(&ch[channel].ddrphy_regs->padctl3, value);
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break;
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@ -979,7 +977,6 @@ void perbit_window_cal(u32 channel, u8 type)
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/* delay DQ from 0 to 15 to get the setup time */
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for (dly = FIRST_DQ_DELAY; dly < MAX_DQDLY_TAPS; dly++) {
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set_dly_factor(channel, STAGE_SETUP, type, dly);
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err_value = dram_k_perbit(channel);
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@ -1015,7 +1012,6 @@ void perbit_window_cal(u32 channel, u8 type)
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/* delay DQS to get the hold time, dq_dly = dqs_dly = 0 is counted */
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/* when we delay dq, so we set first dqs delay to 1 */
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for (dly = (FIRST_DQS_DELAY + 1); dly < max_dqs_taps; dly++) {
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set_dly_factor(channel, STAGE_HOLD, type, dly);
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err_value = dram_k_perbit(channel);
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@ -78,7 +78,6 @@ void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
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pwrap_write_field(addr, vsel, 0x7, 5);
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pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
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}
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void mt6391_enable_reset_when_ap_resets(void)
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@ -362,7 +361,6 @@ static void mt6391_init_setting(void)
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pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
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/* For low power, VIO18 set sleep_en to HW mode */
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pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
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}
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static void mt6391_default_buck_voltage(void)
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@ -289,7 +289,6 @@ static void dramc_rx_input_delay_tracking(u8 chn)
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clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
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(0x3 << 30) | (0x1 << 28) | (0x1 << 23),
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(0x2 << 30) | (0x1 << 28) | (0x1 << 23));
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}
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static void dramc_hw_dqs_gating_tracking(u8 chn)
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@ -537,7 +537,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
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dst_addr = (u8 *)&ch[chn].ao.shu[dst_shuffle] +
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offset;
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write32(dst_addr, read32(src_addr));
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}
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}
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@ -569,7 +568,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
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dst_addr = (u8 *)&ch[chn].phy.shu[dst_shuffle] +
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offset;
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write32(dst_addr, read32(src_addr));
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}
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}
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}
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@ -370,7 +370,6 @@ static const struct apc_infra_peri_dom_8 infra_ao_sys0_devices[] = {
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/* module, AP permission, N/A, SSPM permission, N/A */
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static const struct apc_infra_peri_dom_4 mm_ao_sys0_devices[] = {
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/* 0 */
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DAPC_MM_AO_SYS0_ATTR("IP",
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NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
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@ -1492,7 +1492,6 @@ static void set_infra_ao_apc(uintptr_t base)
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for (j = 0; j < ARRAY_SIZE(infra_ao_sys2_devices[i].d_permission); j++)
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set_module_apc(base + SYS2_D0_APC_0, i, domain_map[j],
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infra_ao_sys2_devices[i].d_permission[j]);
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}
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static void set_peri_ao_apc(uintptr_t base)
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@ -1516,7 +1515,6 @@ static void set_peri_ao_apc(uintptr_t base)
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for (j = 0; j < ARRAY_SIZE(peri_ao_sys1_devices[i].d_permission); j++)
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set_module_apc(base + SYS1_D0_APC_0, i, domain_map[j],
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peri_ao_sys1_devices[i].d_permission[j]);
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}
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static void set_peri2_ao_apc(uintptr_t base)
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@ -1527,7 +1525,6 @@ static void set_peri2_ao_apc(uintptr_t base)
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for (j = 0; j < ARRAY_SIZE(peri2_ao_sys0_devices[i].d_permission); j++)
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set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j],
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peri2_ao_sys0_devices[i].d_permission[j]);
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}
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static void set_peri_par_ao_apc(uintptr_t base)
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@ -1538,7 +1535,6 @@ static void set_peri_par_ao_apc(uintptr_t base)
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for (j = 0; j < ARRAY_SIZE(peri_par_ao_sys0_devices[i].d_permission); j++)
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set_module_apc(base + SYS0_D0_APC_0, i, domain_map[j],
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peri_par_ao_sys0_devices[i].d_permission[j]);
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}
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static void dump_infra_ao_apc(uintptr_t base)
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@ -1599,7 +1595,6 @@ static void dump_peri2_ao_apc(uintptr_t base)
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for (i = 0; i < reg_max; i++)
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printk(BIOS_DEBUG, "[DEVAPC] (PERI2_AO_SYS0)D%d_APC_%d: %#x\n", d,
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i, read32(getreg_domain(base, SYS0_D0_APC_0, d, i)));
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}
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static void dump_peri_par_ao_apc(uintptr_t base)
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@ -1716,7 +1711,6 @@ static void peri_par_init(uintptr_t base)
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/* Master Domain */
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SET32_BITFIELDS(getreg_domain(base, MAS_DOM_0, 0, 4),
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PCIE0_DOM, DOMAIN_2);
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}
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static void fmem_master_init(uintptr_t base)
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@ -44,7 +44,6 @@ enum {
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})
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enum {
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PIN(0, GPIO00, 0, 6, 0x31, 0xe0,
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TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK,
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I2SIN_MCK, I2SO2_MCK, DBG_MON_A0),
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@ -46,7 +46,6 @@ static void infra_master_init(uintptr_t base)
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TWO_BIT_DOM_REMAP_2, MAS_DOMAIN_1,
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TWO_BIT_DOM_REMAP_3, MAS_DOMAIN_3,
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TWO_BIT_DOM_REMAP_4, MAS_DOMAIN_1);
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}
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static void peri_master_init(uintptr_t base)
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@ -37,7 +37,6 @@ enum {
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})
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enum {
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PIN(0, GPIO_00, 1, 0, 0x23, 0x60,
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TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0,
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PERSTN_1, IDDIG_1P, DMIC4_CLK),
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@ -467,7 +467,6 @@ void spm_register_init(void)
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SPM_DVFSRC_ENABLE_LSB, 1);
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write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF);
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write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF);
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}
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void spm_reset_and_init_pcm(void)
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