payloads/external/SeaBIOS: Allow setting buffers below 0xC0000

Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas.  This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.

This will be set to Y unless defaulted to N by the mainboard or
chipset.

Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak

Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/mainboard/intel/mohonpeak/Kconfig

@@ -96,4 +96,12 @@ config UART_FOR_CONSOLE
 	help
 	  The Mohon Peak board uses COM2 (2f8) for the serial console.
 
+config SEABIOS_MALLOC_UPPERMEMORY
+	bool
+	default n
+	help
+	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+	  we put the SeaBIOS buffer area down in the 0x9000 segment.
+
 endif # BOARD_INTEL_MOHONPEAK