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mb/google/brox: Enable PMC pins to work with PD

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Enable SMLINK1 interface for PMC-PD communication to configure Type-C
muxes.

Refer RPL EDS vol 1: 765585.

BUG=b:327622474
BRANCH=None
TEST=Boot image on SKU2 and check PMC-PD working.

Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.com>
This commit is contained in:
Ashish Kumar Mishra 2024-03-12 10:54:38 +05:30 committed by Felix Held
parent e644fa5b7c
commit 4dcf4af010
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/brox/variants/baseboard/brox/gpio.c
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@ -102,8 +102,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B7, NONE),
/* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */
PAD_NC(GPP_B8, NONE),
/* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL (NC) */
PAD_NC(GPP_B11, NONE),
/* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL */
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */
@ -134,10 +134,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C4, NONE),
/* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> SOC_GPP_C5_BOOT_STRAP0 (NC) */
PAD_NC(GPP_C5, NONE),
/* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL (NC) */
PAD_NC(GPP_C6, NONE),
/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */
PAD_NC(GPP_C7, NONE),
/* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST),