sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Restore changes to TCSS ASL

Browse Source 
Change-Id: I8e6093f117f5e5aa453a739b88d1d6fc3fed6598
This commit is contained in:
Jeremy Soller
2020-11-30 14:08:14 -07:00
parent b69fba193b
commit 4dd22de634
2 changed files with 20 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/intel/tigerlake/acpi/tcss_dma.asl
View File

@@ -32,12 +32,20 @@ Method (_S0W, 0x0)
Method (_PR0) Method (_PR0)
{ {
Return (Package() { \_SB.PCI0.D3C }) If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
} }
Method (_PR3) Method (_PR3)
{ {
Return (Package() { \_SB.PCI0.D3C }) If (DUID == 0) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
} }
/* /*
@@ -64,24 +72,6 @@ Method (D3CE, 0, Serialized)
*/ */
Name (SD3C, 0) Name (SD3C, 0)
Method (_PS0, 0, Serialized)
{
If (DUID == 0) {
\_SB.PCI0.TBT0._ON()
} Else {
\_SB.PCI0.TBT1._ON()
}
}
Method (_PS3, 0, Serialized)
{
If (DUID == 0) {
\_SB.PCI0.TBT0._OFF()
} Else {
\_SB.PCI0.TBT1._OFF()
}
}
Method (_DSW, 3) Method (_DSW, 3)
{ {
/* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */ /* If entering Sx (Arg1 > 1), need to skip TCSS D3Cold & TBT RTD3/D3Cold. */

12
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@@ -227,12 +227,20 @@ Method (_S0W, 0x0, NotSerialized)
Method (_PR0) Method (_PR0)
{ {
Return (Package() { \_SB.PCI0.D3C }) If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
} }
Method (_PR3) Method (_PR3)
{ {
Return (Package() { \_SB.PCI0.D3C }) If ((TUID == 0) || (TUID == 1)) {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
} Else {
Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
}
} }
/* /*