Enable UART on lemp10

Change-Id: If82418b9dfcb63dfb7fdd192107d3f6b3d77d3b9

src/mainboard/system76/galp5/devicetree.cb

@@ -282,7 +282,7 @@ chip soc/intel/tigerlake
 		end
 		device ref uart2 on
 			# Debug console
-			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci"
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
 		end
 		device ref pcie_rp5 on
 			# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)

src/mainboard/system76/lemp10/devicetree.cb

@@ -249,6 +249,10 @@ chip soc/intel/tigerlake
 			#TODO Disable ME and HECI
 			register "HeciEnabled" = "1"
 		end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
 		device ref sata on
 			# SATA1 (SSD2)
 			register "SataPortsEnable[1]" = "1"

src/mainboard/system76/lemp10/gpio.h

@@ -10,6 +10,10 @@
 
 /* Pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
+		// UART2_RXD
+		PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
+		// UART2_TXD
+		PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
 };
 
 /* Pad configuration in ramstage. */
@@ -175,9 +179,9 @@ static const struct pad_config gpio_table[] = {
 		// PCH_I2C_SCL
 		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 		// UART2_RXD
-		PAD_NC(GPP_C20, NONE),
+		PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
 		// UART2_TXD
-		PAD_NC(GPP_C21, NONE),
+		PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
 		// GPP_C12_RTD3
 		PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
 		// PCH_GPP_C23