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soc/amd/cezanne: enable LPC decodes if platform uses LPC

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Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67
Signed-off-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Jeremy Soller 2021-11-09 15:21:45 -07:00
parent 5c163bb869
commit 4e29190740
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GPG Key ID: E988B49EE78A7FB1
1 changed files with 9 additions and 0 deletions
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9
src/soc/amd/cezanne/early_fch.c
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@ -21,6 +21,12 @@ static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
};
static void lpc_configure_decodes(void)
{
if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
lpc_enable_port80();
}
static void reset_i2c_peripherals(void)
{
const struct soc_amd_cezanne_config *cfg = config_of_soc();
@ -41,6 +47,9 @@ void fch_pre_init(void)
/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
/* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI
interface hasn't already been set up in verstage on PSP */
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))