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mb/asus/p8z77-m_pro/overridetree.cb: Correct PCIe devices config

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Match PCIe root port allocation and associated comments to
boardview, as follows:

Z77 PCIe ports 1-4: PCIEX16_3 (x4)
Z77 PCIe port 5: PCIEX1_1
Z77 PCIe port 6: RTL8111F LAN
Z77 PCIe port 7: ASM1042 USB3
Z77 PCIe port 8: ASM1061 eSATA
CPU PCIe lanes 1-8: PCIEX16_1
CPU PCIe lanes 9-16: Multiplexed via 4x ASM1480 to PCIEX16_1 lanes 9-16
  and PCIEX16_2 lanes 1-8
(CPU PCIe lanes are not covered by overridetree.cb.)

These are not hardware tested.

Change-Id: I472e28add254ea945b401d1ddfd03f29f46d8fd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Keith Hui
2024-07-22 18:32:35 -04:00
committed by Felix Held
parent 1360d65c98
commit 4ea6f9c288
1 changed files with 4 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
View File

@@ -25,13 +25,10 @@ chip northbridge/intel/sandybridge
}"
device ref pcie_rp1 on end # PCIEX_16_3
device ref pcie_rp2 on end # RTL8111F
device ref pcie_rp3 off end
device ref pcie_rp4 off end
device ref pcie_rp5 off end
device ref pcie_rp6 on end # ASM1042 USB3
device ref pcie_rp7 on end # ASM1061 eSATA
device ref pcie_rp8 off end
device ref pcie_rp5 on end # PCIEX1_1
device ref pcie_rp6 on end # RTL8111F
device ref pcie_rp7 on end # ASM1042 USB3
device ref pcie_rp8 on end # ASM1061 eSATA
device ref lpc on
chip superio/nuvoton/nct6779d