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mb/google/dedede: Add PCIe Root Port Configuration

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Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2020-02-28 16:25:08 -07:00
committed by Patrick Georgi
parent c83c5af3ae
commit 4ebe6dff1a
1 changed files with 25 additions and 0 deletions
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25
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
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@ -76,6 +76,31 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
# PCIE Root Port Configuration
register "PcieRpEnable[0]" = "0"
register "PcieRpEnable[1]" = "0"
register "PcieRpEnable[2]" = "0"
register "PcieRpEnable[3]" = "0"
register "PcieRpEnable[4]" = "0"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieClkSrcUsage[0]" = "0xff"
register "PcieClkSrcUsage[1]" = "0xff"
register "PcieClkSrcUsage[2]" = "0xff"
register "PcieClkSrcUsage[3]" = "0xff"
register "PcieClkSrcUsage[4]" = "0xff"
register "PcieClkSrcUsage[5]" = "0xff"
# PCIE Clock Request to Clock Source Mapping
register "PcieClkSrcClkReq[0]" = "0"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
# Enable EMMC HS400 mode
register "ScsEmmcHs400Enabled" = "1"