arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE

If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.

This also adds board reset for failing to load postcar
from stage cache.

Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/drivers/intel/fsp1_1/Kconfig

@@ -82,10 +82,6 @@ config USE_GENERIC_FSP_CAR_INC
 	  The chipset can select this to use a generic cache_as_ram.inc file
 	  that should be good for all FSP based platforms.
 
-config RESET_ON_INVALID_RAMSTAGE_CACHE
-	bool "Reset the system on S3 wake when ramstage cache invalid."
-	default n
-
 config SKIP_FSP_CAR
 	def_bool n
 	help

src/drivers/intel/fsp2_0/Kconfig

@@ -117,10 +117,6 @@ config FSP_TEMP_RAM_SIZE
 	  stack with coreboot/bootloader.
 	  Sync this value with Platform FSP integration guide recommendation.
 
-config RESET_ON_INVALID_RAMSTAGE_CACHE
-	bool "Reset the system on S3 wake when ramstage cache invalid."
-	default n
-
 config FSP2_0_USES_TPM_MRC_HASH
 	bool
 	depends on TPM1 || TPM2