mb/google/dedede: Enable EC

Perform EC initialization in bootblock and ramstages. Add associated ACPI
configuration.

BUG=b:144768001
TEST=Build Test.

Change-Id: Ib31ae190818c8870bdd46ea6c3d9ca70dc0485cc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/dedede/Kconfig

@@ -1,5 +1,7 @@
 config BOARD_GOOGLE_BASEBOARD_DEDEDE
 	def_bool n
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select MAINBOARD_HAS_CHROMEOS
@@ -14,6 +16,8 @@ config BASEBOARD_DEDEDE_LAPTOP
 config CHROMEOS
 	bool
 	default y
+	select EC_GOOGLE_CHROMEEC_SWITCHES
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
 	select VBOOT_LID_SWITCH
 
 config DEVICETREE

src/mainboard/google/dedede/Makefile.inc

@@ -7,6 +7,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
+ramstage-y += ec.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 

src/mainboard/google/dedede/chromeos.c

@@ -23,18 +23,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
 
-int get_lid_switch(void)
-{
-	/* TODO: use Chrome EC switches when EC support is added */
-	return 1;
-}
-
-int get_recovery_mode_switch(void)
-{
-	/* TODO: use Chrome EC switches when EC support is added */
-	return 0;
-}
-
 int get_write_protect_state(void)
 {
 	/* No write protect */

src/mainboard/google/dedede/dsdt.asl

@@ -7,6 +7,7 @@
  */
 
 #include <arch/acpi.h>
+#include <variant/ec.h>
 #include <variant/gpio.h>
 
 DefinitionBlock(
@@ -41,4 +42,12 @@ DefinitionBlock(
 	/* Chipset specific sleep states */
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+        }
 }

src/mainboard/google/dedede/ec.c

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc_lib.h>
+#include <variant/ec.h>
+
+void mainboard_ec_init(void)
+{
+	static const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	printk(BIOS_ERR, "mainboard: EC init\n");
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}

src/mainboard/google/dedede/mainboard.c

@@ -9,6 +9,7 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <ec/ec.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 static void mainboard_init(void *chip_info)
@@ -20,6 +21,11 @@ static void mainboard_init(void *chip_info)
 	gpio_configure_pads(pads, num);
 }
 
+static void mainboard_dev_init(struct device *dev)
+{
+	mainboard_ec_init();
+}
+
 static unsigned long mainboard_write_acpi_tables(
 		struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
 {
@@ -28,6 +34,7 @@ static unsigned long mainboard_write_acpi_tables(
 
 static void mainboard_enable(struct device *dev)
 {
+	dev->ops->init = mainboard_dev_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }

src/mainboard/google/dedede/smihandler.c

@@ -8,10 +8,13 @@
 
 #include <baseboard/variants.h>
 #include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
 #include <intelblocks/smihandler.h>
+#include <variant/ec.h>
 
 void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 {
+	/* TODO: Process SMI events from GPI */
 }
 
 void mainboard_smi_sleep(u8 slp_typ)
@@ -21,9 +24,14 @@ void mainboard_smi_sleep(u8 slp_typ)
 
 	pads = variant_sleep_gpio_table(&num);
 	gpio_configure_pads(pads, num);
+
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+				MAINBOARD_EC_S5_WAKE_EVENTS);
 }
 
 int mainboard_smi_apmc(u8 apmc)
 {
+	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+				MAINBOARD_EC_SMI_EVENTS);
 	return 0;
 }

src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h

@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)              |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3/S0ix with:
+ * 1. Lid open
+ * 2. Power button
+ * 3. Key press
+ * 4. Mode change
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN      GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE     /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE       /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
+
+#endif /* __BASEBOARD_EC_H__ */

src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h

@@ -12,4 +12,10 @@
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
 #endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/google/dedede/variants/dedede/include/variant/ec.h

@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif