mb/google/dedede: Enable building for Chrome OS

Enable building for Chrome OS and add associated ACPI configuration.

BUG=b:144768001
TEST=Build Test

Change-Id: Ibb94849a903e4d4364d817de8988a430cd717e4c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian
2020-01-06 23:40:59 -07:00
committed by Furquan Shaikh
parent d60386ef2f
commit b7b11475c1
7 changed files with 79 additions and 1 deletions

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@@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE
@@ -10,6 +11,11 @@ config BASEBOARD_DEDEDE_LAPTOP
def_bool n
select SYSTEM_TYPE_LAPTOP
config CHROMEOS
bool
default y
select VBOOT_LID_SWITCH
config DEVICETREE
string
default "variants/baseboard/devicetree.cb"

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@@ -1,5 +1,11 @@
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

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@@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_lid_switch(void)
{
/* TODO: use Chrome EC switches when EC support is added */
return 1;
}
int get_recovery_mode_switch(void)
{
/* TODO: use Chrome EC switches when EC support is added */
return 0;
}
int get_write_protect_state(void)
{
/* No write protect */
return 0;
}
void mainboard_chromeos_acpi_generate(void)
{
const struct cros_gpio *gpios;
size_t num;
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}

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@@ -35,6 +35,9 @@ DefinitionBlock(
}
}
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>

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@@ -9,6 +9,7 @@
#include <arch/acpi.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info)
{
@@ -28,7 +29,7 @@ static unsigned long mainboard_write_acpi_tables(
static void mainboard_enable(struct device *dev)
{
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt_generator = NULL;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

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@@ -9,6 +9,7 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
@@ -41,3 +42,12 @@ const struct pad_config *__weak variant_sleep_gpio_table(size_t *num)
*num = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
};
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}

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@@ -18,5 +18,6 @@
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_sleep_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
#endif /*__BASEBOARD_VARIANTS_H__ */