sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya/var/vell: Enable SaGv

Browse Source 
Enable SaGv support for vell

BUG=b:208719081
TEST=FW_NAME=vell emerge-brya coreboot

Change-Id: I01e3da449e2cf53278f625ca265d09f7a1869ef7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Robert Chen
2022-01-03 09:23:58 +08:00
committed by Felix Held
parent 6a3ecc508a
commit 502a761221
2 changed files with 3 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/brya/variants/vell/memory.c
View File

@@ -65,7 +65,8 @@ static const struct mb_cfg baseboard_memcfg = {
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
}, },
.ect = true, /* Enable Early Command Training */ .ect = false, /* Early Command Training */
.UserBd = BOARD_TYPE_ULT_ULX_T4,
.lp5x_config = { .lp5x_config = {
.ccc_config = 0xff, .ccc_config = 0xff,

1
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@@ -32,6 +32,7 @@ chip soc/intel/alderlake
register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_3]" = "0"
register "gpio_pm[COMM_4]" = "0" register "gpio_pm[COMM_4]" = "0"
register "gpio_pm[COMM_5]" = "0" register "gpio_pm[COMM_5]" = "0"
register "SaGv" = "SaGv_Enabled"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+