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mb/*: Add consolidated USB port config for SNB+MRC boards

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For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.

These get hooked up in a separate patch.

Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui
2024-02-05 16:44:38 -05:00
committed by Martin L Roth
parent 1acb3e118b
commit 51a57eb5ea
13 changed files with 210 additions and 2 deletions
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16
src/mainboard/google/parrot/devicetree.cb
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@@ -56,6 +56,22 @@ chip northbridge/intel/sandybridge
register "sata_port_map" = "0x1"
register "usb_port_config" = "{
{0, 0, -1}, /* P0: Empty */
{1, 0, 0}, /* P1: Left USB 1 (OC0) */
{1, 0, 1}, /* P2: Left USB 2 (OC1) */
{1, 0, 1}, /* P3: Left USB 3 (OC1) */
{0, 0, -1}, /* P4-P7: Empty */
{0, 0, -1},
{0, 0, -1},
{0, 0, -1},
/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
{1, 0, -1}, /* P8: MiniPCIe (WLAN) (no OC) */
{0, 0, -1}, /* P9: Empty */
{1, 0, -1}, /* P10: Camera (no OC) */
{0, 0, -1}, {0, 0, -1}, {0, 0, -1}
}"
# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
register "gen1_dec" = "0x0004fd61"
register "gen2_dec" = "0x00040069"