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src/soc: Fix various typos

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These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
2018-02-12 12:24:25 +01:00
committed by Martin Roth
parent e33f120cb8
commit 5268b76801
44 changed files with 82 additions and 82 deletions
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4
src/soc/imgtec/pistachio/ddr3_init.c
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@ -303,7 +303,7 @@ int init_ddr3(void)
write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
/* TRAS : Activate to Precharge cmd time 15 45ns / 2.5ns = 18d */
write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
/* TRC : Min. ROW cylce time 21
/* TRC : Min. ROW cycle time 21
* 57.5ns / 2.5ns = 23d Playing safe 24
*/
write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
@ -428,7 +428,7 @@ int init_ddr3(void)
*/
write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
/* Memory initilization */
/* Memory initialization */
/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
* 3:0 cmd_opcode PREA 00001
* 16:4 cmd_addr 0