Merge remote-tracking branch 'upstream/master' into galp5

Change-Id: I718ce2ea23c20405a0392793361cf3e52e864276

Documentation/mainboard/clevo/n130wu/index.md

@@ -0,0 +1,47 @@
+# Clevo N130WU
+
+## Hardware
+### Technology
+```eval_rst
++------------------+--------------------------------+
+| CPU              | Intel i7-8550U                 |
++------------------+--------------------------------+
+| PCH              | Intel Sunrise Point LP         |
++------------------+--------------------------------+
+| EC / Super IO    | ITE IT8587E                    |
++------------------+--------------------------------+
+| Coprocessor      | Intel ME                       |
++------------------+--------------------------------+
+```
+
+### Flash chip
+```eval_rst
++---------------------+-----------------+
+| Type                | Value           |
++=====================+=================+
+| Model               | GD25Q64B        |
++---------------------+-----------------+
+| Socketed flash      | no              |
++---------------------+-----------------+
+| Size                | 8 MiB           |
++---------------------+-----------------+
+| In circuit flashing | Yes             |
++---------------------+-----------------+
+| Package             | SOIC-8          |
++---------------------+-----------------+
+| Write protection    | No              |
++---------------------+-----------------+
+| Dual BIOS feature   | No              |
++---------------------+-----------------+
+| Internal flashing   | Yes             |
++---------------------+-----------------+
+```
+
+## Board status
+### Working
+### Not Working
+### Work in progress
+### Untested
+
+## Also known as
+* TUXEDO InfinityBook Pro 13 v3

Documentation/mainboard/index.md

@@ -26,6 +26,10 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
 
+## Clevo
+
+- [N130WU / N131WU](clevo/n130wu/index.md)
+
 ## Dell
 
 - [OptiPlex 9010 SFF](dell/optiplex_9010.md)

Documentation/releases/coreboot-4.13-relnotes.md

@@ -1,14 +1,89 @@
-Upcoming release - coreboot 4.13
+coreboot 4.13
 ================================
 
-The 4.13 release is planned for November 2020.
+coreboot 4.13 was released on November 20th, 2020.
 
-Update this document with changes that should be in the release notes.
+Since 4.12 there were 4200 new commits by over 234 developers.
+Of these, about 72 contributed to coreboot for the first time.
 
-* Please use Markdown.
+Thank you to all developers who again helped made coreboot better
-* See the past few release notes for the general format.
+than ever, and a big welcome to our new contributors!
-* The chip and board additions and removals will be updated right
+
-  before the release, so those do not need to be added.
+New mainboards
+--------------
+
+- Acer G43T-AM3
+- AMD Cereme
+- Asus A88XM-E FM2+
+- Biostar TH61-ITX
+- BostenTech GBYT4
+- Clevo L140CU/L141CU
+- Dell OptiPlex 9010
+- Example Min86 (fake board)
+- Google Ambassador
+- Google Asurada
+- Google Berknip
+- Google Boldar
+- Google Boten
+- Google Burnet
+- Google Cerise
+- Google Coachz
+- Google Dalboz
+- Google Dauntless
+- Google Delbin
+- Google Dirinboz
+- Google Dooly
+- Google Drawcia
+- Google Eldrid
+- Google Elemi
+- Google Esche
+- Google Ezkinil
+- Google Faffy
+- Google Fennel
+- Google Genesis
+- Google Hayato
+- Google Lantis
+- Google Lindar
+- Google Madoo
+- Google Magolor
+- Google Metaknight
+- Google Morphius
+- Google Noibat
+- Google Pompom
+- Google Shuboz
+- Google Stern
+- Google Terrador
+- Google Todor
+- Google Trembyle
+- Google Vilboz
+- Google Voema
+- Google Volteer2
+- Google Voxel
+- Google Willow
+- Google Woomax
+- Google Wyvern
+- HP EliteBook 2560p
+- HP EliteBook Folio 9480m
+- HP ProBook 6360b
+- Intel Alderlake-P RVP
+- Kontron COMe-bSL6
+- Lenovo ThinkPad X230s
+- Open Compute Project DeltaLake
+- Prodrive Hermes
+- Purism Librem Mini
+- Purism Librem Mini v2
+- Siemens Chili
+- Supermicro X11SSH-F
+- System76 lemp9
+
+Removed mainboards
+------------------
+
+- Google Cheza
+- Google DragonEgg
+- Google Ripto
+- Google Sushi
+- Open Compute Project SonoraPass
 
 Significant changes
 -------------------
@@ -62,11 +137,11 @@ the platforms. More details about the tools are added in
 
 ### New version of SMM loader
 
-A new version of the SMM loader which accomodates platforms with over 32 CPU
+A new version of the SMM loader which accommodates platforms with over 32
 CPU threads.  The existing version of SMM loader uses a 64K code/data
 segment and only a limited number of CPU threads can fit into one segment
 (because of save state, STM, other features, etc). This loader extends beyond
-the 64K segment to accomodate additional CPUs and in theory allows as many
+the 64K segment to accommodate additional CPUs and in theory allows as many
 CPU threads as possible limited only by SMRAM space and not by 64K. By default
 this loader version is disabled. Please see cpu/x86/Kconfig for more info.
 
@@ -81,11 +156,81 @@ more info.
 
 ### Initial support for x86_64
 
-The x86_64 code support has been revived and enabled for qemu. While it started
+The x86_64 code support has been revived and enabled for QEMU. While it started
 as PoC and the only supported platform is an emulator, there's interest in
 enabling additional platforms. It would allow to access more than 4GiB of memory
 at runtime and possibly brings optimised code for faster execution times.
 It still needs changes in assembly, fixed integer to pointer conversions in C,
 wrappers for blobs, support for running Option ROMs, among other things.
 
-### Add significant changes here
+### Preparations to minimize enabling PCI bus mastering
+
+For security reasons, bus mastering should be enabled as late as possible. In
+coreboot, it's usually not necessary and payloads should only enable it for
+devices they use. Since not all payloads enable bus mastering properly yet,
+some Kconfig options were added as an intermediate step to give some sort of
+"backwards compatibility", which allow enabling or disabling bus mastering by
+groups.
+
+Currently available groups are:
+
+* PCI bridges
+* Any devices
+
+For now, "Any devices" is enabled by default to keep the traditional behaviour,
+which also includes all other options. This is currently necessary, for instance,
+for libpayload-based payloads as the drivers don't enable bus mastering for PCI
+bridges.
+
+Exceptional cases, that may still need early bus master enabling in the future,
+should get their own per-reason Kconfig option. Ideally before the next release.
+
+### Early runtime configurability of the console log level
+
+Traditionally, we didn't allow the log level of the `romstage` console
+to be changed at runtime (e.g. via `get_option()`). It turned out that
+the technical constraints for this (no global variables in `romstage`)
+vanished long ago, though. The new behaviour is to query `get_option()`
+now from the second stage that uses the console on. In other words, if
+the `bootblock` already enables the console, the `romstage` log level
+can be changed via `get_option()`. Keeping the log level of the first
+console static ensures that we can see console output even if there's
+a bug in the more involved code to query options.
+
+### Resource allocator v4
+
+A new revision of resource allocator v4 is now added to coreboot that supports
+mutiple ranges for allocating resources. Unlike the previous allocator (v3), it does
+not use the topmost available window for allocation. Instead, it uses the first
+window within the address space that is available and satisfies the resource request.
+This allows utilization of the entire available address space and also allows
+allocation above the 4G boundary. The old resource allocator v3 is still retained for
+some AMD platforms that do not conform to the requirements of the allocator.
+
+Deprecations
+------------
+
+### PCI bus master configuration options
+
+In order to minimize the usage of PCI bus mastering, the options we introduced in
+this release will be dropped in a future release again. For more details, please
+see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot).
+
+### Resource allocator v3
+
+Resource allocator v3 is retained in coreboot tree because the following platforms
+do not conform to the requirements of the resource allocation i.e. not all the fixed
+resources of the platform are provided during the `read_resources()` operation:
+
+* northbridge/amd/pi/00630F01
+* northbridge/amd/pi/00730F01
+* northbridge/amd/pi/00660F01
+* northbridge/amd/agesa/family14
+* northbridge/amd/agesa/family15tn
+* northbridge/amd/agesa/family16kb
+
+In order to have a single unified allocator in coreboot, this notice is being added
+to ensure that the platforms listed above are fixed before the next release. If there
+is interest in maintaining support for these platforms beyond the next release,
+please ensure that the platforms are fixed to conform to the expectations of resource
+allocation.

Documentation/releases/coreboot-4.14-relnotes.md

@@ -0,0 +1,16 @@
+Upcoming release - coreboot 4.14
+================================
+
+The 4.14 release is planned for May 2021.
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here

Documentation/releases/index.md

@@ -13,6 +13,7 @@ Release notes for previous releases
 * [4.10 - July 2019](coreboot-4.10-relnotes.md)
 * [4.11 - November 2019](coreboot-4.11-relnotes.md)
 * [4.12 - May 2020](coreboot-4.12-relnotes.md)
+* [4.13 - November 2020](coreboot-4.13-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -24,4 +25,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -8,6 +8,8 @@
 - Facebook Monolith
 
 ## Google
+- Asurada
+- Hayato
 - Auron_Paine (Acer C740 Chromebook)
 - Auron_Yuna (Acer Chromebook 15 (C910/CB5-531))
 - Buddy (Acer Chromebase 24)
@@ -34,7 +36,6 @@
 - Daisy (Samsung Chromebook (2012))
 - Deltan
 - Deltaur
-- DragonEgg
 - Drallion
 - Eve (Google Pixelbook)
 - Fizz
@@ -57,9 +58,12 @@
 - Rainier
 - Akemi
 - Dratini
+- Duffy Legacy (32MB)
 - Duffy
+- Faffy
 - Hatch
 - Jinlon
+- Kaisa Legacy (32MB)
 - Kaisa
 - Kohaku
 - Kindred
@@ -67,10 +71,14 @@
 - Mushu
 - Palkia
 - Nightfury
+- Noibat
 - Puff
 - Helios_Diskswap
 - Stryke
-- Sushi
+- Wyvern
+- Dooly
+- Ambassador
+- Genesis
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
@@ -90,6 +98,12 @@
 - Juniper
 - Kappa
 - Damu
+- Cerise
+- Stern
+- Willow
+- Esche
+- Burnet
+- Fennel
 - Link (Google Chromebook Pixel (2013))
 - Mistral
 - Nyan
@@ -100,13 +114,13 @@
 - Hana (Lenovo N23 Yoga Chromebook)
 - Parrot (Acer C7/C710 Chromebook)
 - Peach Pit (Samsung Chromebook 2 11\")
-- Atlas
+- Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
-- Nautilus
+- Nautilus (Samsung Chromebook Plus (V2 / LTE))
-- Nocturne
+- Nocturne (Google Pixel Slate)
-- Rammus
+- Rammus (Asus Chromebook C425, Flip C433, Flip C434)
-- Soraka
+- Soraka (HP Chromebook x2)
 - Banjo (Acer Chromebook 15 (CB3-531))
 - Candy (Dell Chromebook 11 3120)
 - Clapper (Lenovo N20 Chromebook)
@@ -138,10 +152,11 @@
 - Smaug (Google Pixel C)
 - Storm (OnHub Router TGR1900)
 - Stout (Lenovo Thinkpad X131e Chromebook)
-- Trogdor
-- Lazor
 - Bubs
 - Coachz
+- Lazor
+- Pompom
+- Trogdor
 - Veyron_Jaq (Haier Chromebook 11)
 - Veyron_Jerry (Hisense Chromebook 11)
 - Veyron_Mighty (Haier Chromebook 11(edu))
@@ -149,11 +164,22 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
+- Dalboz
+- Vilboz
+- Ezkinil
+- Morphius
+- Trembyle
+- Berknip
+- Woomax
+- Dirinboz
+- Shuboz
 
 ## HP
 - Z220 SFF Workstation
 
 ## Intel
+- Alderlake-P RVP
+- Alderlake-P RVP with Chrome EC
 - Basking Ridge CRB
 - Cannonlake U LPDDR4 RVP
 - Cannonlake Y LPDDR4 RVP
@@ -206,6 +232,7 @@
 - ThinkPad X1
 - ThinkPad X230
 - ThinkPad X230t
+- ThinkPad X230s
 - ThinkPad X60 / X60s / X60t
 
 ## OpenCellular
@@ -226,6 +253,7 @@
 ## Supermicro
 - X11SSH-TF
 - X11SSM-F
+- X11SSH-F
 
 ## UP
 - Squared

MAINTAINERS

@@ -511,7 +511,6 @@ M:	David Guckian <david.guckian@intel.com>
 S:	Odd Fixes
 F:	src/mainboard/intel/harcuvar/
 F:	src/soc/intel/denverton_ns/
-F:	src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
 
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
@@ -529,6 +528,14 @@ F:	src/drivers/intel/fsp2_0/
 # Systems on a Chip
 ################################################################################
 
+AMD Picasso
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
+M:	Felix Held <felix-coreboot@felixheld.de>
+M:	Jason Glenesk <jason.glenesk@gmail.com>
+S:	Maintained
+F:	src/soc/amd/picasso
+F:	src/vendorcode/amd/fsp/picasso
+
 INTEL APOLLOLAKE_SOC
 M:	Andrey Petrov <andrey.petrov@gmail.com>
 S:	Maintained

Makefile.inc

@@ -35,7 +35,8 @@ COREBOOT_EXPORTS += KERNELVERSION
 # Basic component discovery
 MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR))
 VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
-COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR
+CARRIER_DIR:=$(call strip_quotes,$(CONFIG_CARRIER_DIR))
+COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR CARRIER_DIR
 
 ## Final build results, which CBFSTOOL uses to create the final
 ## rom image file, are placed under $(objcbfs).
@@ -1134,22 +1135,6 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE
 # file (filled with \377 = 0xff) and copy the CBFS image over it.
 	dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp
 	dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
-ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
-ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
-ifneq ($(CONFIG_UPDATE_IMAGE),y)
-	@printf "    SeaBIOS    Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
-	$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup
-endif
-endif
-endif
-ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
-	@printf "    SeaBIOS    Add sercon-port file\n"
-	$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
-endif
-ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
-	@printf "    SeaBIOS    Thread optionroms\n"
-	$(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads
-endif
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
 ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)

configs/config.scaleway_tagada

@@ -0,0 +1,15 @@
+CONFIG_VENDOR_SCALEWAY=y
+CONFIG_BOARD_SCALEWAY_TAGADA=y
+CONFIG_CBFS_SIZE=0x400000
+CONFIG_CONSOLE_POST=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_IQAT_ENABLE is not set
+CONFIG_LEGACY_UART_MODE=y
+CONFIG_USE_DENVERTON_NS_FSP_CAR=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd"
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_BOOT_STATE=y

payloads/external/Makefile.inc

@@ -106,6 +106,31 @@ bootorder-file := $(strip $(CONFIG_SEABIOS_BOOTORDER_FILE))
 bootorder-type := raw
 endif
 
+ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
+ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
+ifneq ($(CONFIG_UPDATE_IMAGE),y)
+INTERMEDIATE+=seabios_ps2_timeout
+seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL)
+	@printf "    SeaBIOS    Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
+	$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup
+endif
+endif
+endif
+
+ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
+INTERMEDIATE+=seabios_sercon
+seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL)
+	@printf "    SeaBIOS    Add sercon-port file\n"
+#	$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
+endif
+
+ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
+INTERMEDIATE+=seabios_thread_optionroms
+seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL)
+	@printf "    SeaBIOS    Thread optionroms\n"
+	$(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads
+endif
+
 # Depthcharge
 
 payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL)

payloads/libpayload/drivers/i8042/i8042.c

@@ -159,7 +159,7 @@ static u8 i8042_wait_cmd_rdy(void)
  */
 static u8 i8042_wait_data_rdy(void)
 {
-	int retries = 10000;
+	int retries = 30000;
 	while (retries-- && !(read_status() & OBF))
 		udelay(50);
 

src/acpi/Makefile.inc

@@ -3,6 +3,7 @@
 ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
 
 ramstage-y += acpi.c
+ramstage-y += acpi_pm.c
 ramstage-y += acpigen.c
 ramstage-y += acpigen_dptf.c
 ramstage-y += acpigen_dsm.c
@@ -15,6 +16,8 @@ ramstage-y += pld.c
 ramstage-y += sata.c
 ramstage-y += soundwire.c
 
+postcar-y += acpi_pm.c
+
 ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
 endif

src/acpi/acpi.c

@@ -1251,14 +1251,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	/* should be 0 ACPI 3.0 */
 	fadt->reserved = 0;
 
-	if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) ||
+	fadt->preferred_pm_profile = acpi_get_preferred_pm_profile();
-	    CONFIG(SYSTEM_TYPE_LAPTOP))
-		fadt->preferred_pm_profile = PM_MOBILE;
-	else if (CONFIG(SYSTEM_TYPE_DETACHABLE) ||
-		 CONFIG(SYSTEM_TYPE_TABLET))
-		fadt->preferred_pm_profile = PM_TABLET;
-	else
-		fadt->preferred_pm_profile = PM_DESKTOP;
 
 	arch_fill_fadt(fadt);
 
@@ -1626,7 +1619,7 @@ void *acpi_find_wakeup_vector(void)
 	void *wake_vec;
 	int i;
 
-	if (!acpi_is_wakeup())
+	if (!acpi_is_wakeup_s3())
 		return NULL;
 
 	printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n");

src/acpi/acpi_pm.c

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <romstage_handoff.h>
+#include <smbios.h>
+
+/* This is filled with acpi_handoff_wakeup_s3() call early in ramstage. */
+static int acpi_slp_type = -1;
+
+static void acpi_handoff_wakeup(void)
+{
+	if (acpi_slp_type < 0) {
+		if (romstage_handoff_is_resume()) {
+			printk(BIOS_DEBUG, "S3 Resume\n");
+			acpi_slp_type = ACPI_S3;
+		} else {
+			printk(BIOS_DEBUG, "Normal boot\n");
+			acpi_slp_type = ACPI_S0;
+		}
+	}
+}
+
+int acpi_handoff_wakeup_s3(void)
+{
+	acpi_handoff_wakeup();
+	return (acpi_slp_type == ACPI_S3);
+}
+
+void __weak mainboard_suspend_resume(void)
+{
+}
+
+/* Default mapping to ACPI FADT preferred_pm_profile field. */
+uint8_t acpi_get_preferred_pm_profile(void)
+{
+	switch (smbios_mainboard_enclosure_type()) {
+	case SMBIOS_ENCLOSURE_LAPTOP:
+	case SMBIOS_ENCLOSURE_CONVERTIBLE:
+		return PM_MOBILE;
+	case SMBIOS_ENCLOSURE_DETACHABLE:
+	case SMBIOS_ENCLOSURE_TABLET:
+		return PM_TABLET;
+	case SMBIOS_ENCLOSURE_DESKTOP:
+		return PM_DESKTOP;
+	case SMBIOS_ENCLOSURE_UNKNOWN:
+	default:
+		return PM_UNSPECIFIED;
+	}
+}

src/arch/x86/Kconfig

@@ -88,16 +88,6 @@ config AP_IN_SIPI_WAIT
 	default n
 	depends on ARCH_X86 && SMP
 
-config X86_RESET_VECTOR
-	hex
-	depends on ARCH_X86
-	default 0xfffffff0
-	help
-	  Specify the location of the x86 reset vector.  In traditional devices
-	  this must match the architectural reset vector to produce a bootable
-	  image.  Nontraditional designs may use this to position the reset
-	  vector into its desired location.
-
 config RESET_VECTOR_IN_RAM
 	bool
 	depends on ARCH_X86

src/arch/x86/Makefile.inc

@@ -158,7 +158,6 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
 
 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
 
-romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 romstage-y += boot.c
 romstage-y += post.c
 # gdt_init.S is included by entry32.inc when romstage is the first C
@@ -202,7 +201,6 @@ $(eval $(call create_class_compiler,postcar,x86_64))
 endif
 postcar-generic-ccopts += -D__POSTCAR__
 
-postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 postcar-y += boot.c
 postcar-y += post.c
 postcar-y += gdt_init.S

src/arch/x86/acpi_s3.c

@@ -8,45 +8,6 @@
 #include <cpu/x86/smm.h>
 #include <fallback.h>
 #include <timestamp.h>
-#include <romstage_handoff.h>
-
-#if ENV_RAMSTAGE || ENV_POSTCAR
-
-/* This is filled with acpi_is_wakeup() call early in ramstage. */
-static int acpi_slp_type = -1;
-
-static void acpi_handoff_wakeup(void)
-{
-	if (acpi_slp_type < 0) {
-		if (romstage_handoff_is_resume()) {
-			printk(BIOS_DEBUG, "S3 Resume\n");
-			acpi_slp_type = ACPI_S3;
-		} else {
-			printk(BIOS_DEBUG, "Normal boot\n");
-			acpi_slp_type = ACPI_S0;
-		}
-	}
-}
-
-int acpi_is_wakeup(void)
-{
-	acpi_handoff_wakeup();
-	/* Both resume from S2 and resume from S3 restart at CPU reset */
-	return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2);
-}
-
-int acpi_is_wakeup_s3(void)
-{
-	acpi_handoff_wakeup();
-	return (acpi_slp_type == ACPI_S3);
-}
-
-int acpi_is_wakeup_s4(void)
-{
-	acpi_handoff_wakeup();
-	return (acpi_slp_type == ACPI_S4);
-}
-#endif /* ENV_RAMSTAGE */
 
 #define WAKEUP_BASE 0x600
 
@@ -55,22 +16,6 @@ asmlinkage void (*acpi_do_wakeup)(uintptr_t vector) = (void *)WAKEUP_BASE;
 extern unsigned char __wakeup;
 extern unsigned int __wakeup_size;
 
-static void acpi_jump_to_wakeup(void *vector)
-{
-	/* Copy wakeup trampoline in place. */
-	memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
-
-	set_boot_successful();
-
-	timestamp_add_now(TS_ACPI_WAKE_JUMP);
-
-	acpi_do_wakeup((uintptr_t)vector);
-}
-
-void __weak mainboard_suspend_resume(void)
-{
-}
-
 void __noreturn acpi_resume(void *wake_vec)
 {
 	/* Restore GNVS pointer in SMM if found. */
@@ -79,8 +24,15 @@ void __noreturn acpi_resume(void *wake_vec)
 	/* Call mainboard resume handler first, if defined. */
 	mainboard_suspend_resume();
 
+	/* Copy wakeup trampoline in place. */
+	memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
+
+	set_boot_successful();
+
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+
 	post_code(POST_OS_RESUME);
-	acpi_jump_to_wakeup(wake_vec);
+	acpi_do_wakeup((uintptr_t)wake_vec);
 
 	die("Failed the jump to wakeup vector\n");
 }

src/arch/x86/car.ld

@@ -11,18 +11,17 @@
 	/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
 	 * aligned when using this option. */
 	_pagetables = . ;
-	.  += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
+	. += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
 	_epagetables = . ;
 #endif
+#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
 	/* Vboot work buffer only needs to be available when verified boot
 	 * starts in bootblock. */
-#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
 	VBOOT2_WORK(., 12K)
 #endif
-	/* Vboot measured boot TCPA log measurements.
-	 * Needs to be transferred until CBMEM is available
-	 */
 #if CONFIG(TPM_MEASURED_BOOT)
+	/* Vboot measured boot TCPA log measurements.
+	 * Needs to be transferred until CBMEM is available */
 	TPM_TCPA_LOG(., 2K)
 #endif
 	/* Stack for CAR stages. Since it persists across all stages that
@@ -33,8 +32,8 @@
 	_ecar_stack = .;
 	/* The pre-ram cbmem console as well as the timestamp region are fixed
 	 * in size. Therefore place them above the car global section so that
-         * multiple stages (romstage and verstage) have a consistent
+	 * multiple stages (romstage and verstage) have a consistent
-         * link address of these shared objects. */
+	 * link address of these shared objects. */
 	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
 #if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	. = ALIGN(32);
@@ -55,8 +54,8 @@
 
 	_car_ehci_dbg_info = .;
 	/* Reserve sizeof(struct ehci_dbg_info). */
-        . += 80;
+	. += 80;
-        _ecar_ehci_dbg_info = .;
+	_ecar_ehci_dbg_info = .;
 
 	/* _bss and _ebss provide symbols to per-stage
 	 * variables that are not shared like the timestamp and the pre-ram
@@ -110,7 +109,7 @@ _rom_mtrr_base = _rom_mtrr_mask;
 . = 0xffffff00;
 .illegal_globals . : {
 	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
-		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
+	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");

src/arch/x86/id.ld

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 SECTIONS {
-	. = (CONFIG_X86_RESET_VECTOR - CONFIG_ID_SECTION_OFFSET) + 0x10 - (__id_end - __id_start);
+	. = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1;
 	.id (.): {
 		KEEP(*(.id))
 	}

src/arch/x86/memlayout.ld

@@ -28,7 +28,7 @@ SECTIONS
 
 	#include "car.ld"
 #elif ENV_BOOTBLOCK
-	BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
+	BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1,
 			CONFIG_C_ENV_BOOTBLOCK_SIZE)
 
 	#include "car.ld"

src/arch/x86/smbios.c

@@ -1068,7 +1068,7 @@ static int smbios_write_type17(unsigned long *current, int *handle, int type16)
 	return totallen;
 }
 
-static int smbios_write_type19(unsigned long *current, int *handle)
+static int smbios_write_type19(unsigned long *current, int *handle, int type16)
 {
 	struct smbios_type19 *t = (struct smbios_type19 *)*current;
 	int len = sizeof(struct smbios_type19);
@@ -1084,6 +1084,7 @@ static int smbios_write_type19(unsigned long *current, int *handle)
 	t->type = SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS;
 	t->length = len - 2;
 	t->handle = *handle;
+	t->memory_array_handle = type16;
 
 	for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
 		if (meminfo->dimm[i].dimm_size > 0) {
@@ -1335,7 +1336,7 @@ unsigned long smbios_write_tables(unsigned long current)
 	const int type16 = handle;
 	update_max(len, max_struct_size, smbios_write_type16(&current, &handle));
 	update_max(len, max_struct_size, smbios_write_type17(&current, &handle, type16));
-	update_max(len, max_struct_size, smbios_write_type19(&current, &handle));
+	update_max(len, max_struct_size, smbios_write_type19(&current, &handle, type16));
 	update_max(len, max_struct_size, smbios_write_type32(&current, handle++));
 
 	update_max(len, max_struct_size, smbios_walk_device_tree(all_devices,

src/commonlib/include/commonlib/timestamp_serialized.h

@@ -52,6 +52,8 @@ enum timestamp_id {
 	TS_SELFBOOT_JUMP = 99,
 	TS_START_POSTCAR = 100,
 	TS_END_POSTCAR = 101,
+	TS_DELAY_START = 110,
+	TS_DELAY_END = 111,
 
 	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
 	TS_START_COPYVER = 501,
@@ -177,6 +179,8 @@ static const struct timestamp_id_to_name {
 	{ TS_LOAD_PAYLOAD,	"load payload" },
 	{ TS_ACPI_WAKE_JUMP,	"ACPI wake jump" },
 	{ TS_SELFBOOT_JUMP,	"selfboot jump" },
+	{ TS_DELAY_START,	"Forced delay start" },
+	{ TS_DELAY_END,		"Forced delay end" },
 
 	{ TS_START_COPYVER,	"starting to load verstage" },
 	{ TS_END_COPYVER,	"finished loading verstage" },

src/cpu/amd/agesa/family14/model_14_init.c

@@ -52,7 +52,7 @@ static void model_14_init(struct device *dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
+	if (acpi_is_wakeup_s3())
 		restore_mtrr();
 
 	x86_mtrr_check();

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -51,7 +51,7 @@ static void model_15_init(struct device *dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
+	if (acpi_is_wakeup_s3())
 		restore_mtrr();
 
 	x86_mtrr_check();

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -49,7 +49,7 @@ static void model_16_init(struct device *dev)
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
+	if (acpi_is_wakeup_s3())
 		restore_mtrr();
 
 	x86_mtrr_check();

src/cpu/x86/16bit/reset16.ld

@@ -1,13 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* _RESET_VECTOR: typically the top of the ROM */
+/*
+ *      _ROMTOP                 : The top of the ROM used where we
+ *				  need to put the reset vector.
+ */
 
 SECTIONS {
 	/* Trigger an error if I have an unuseable start address */
-	_TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+	_bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");
-	_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
+	_ROMTOP = 0xfffffff0;
-
+	. = _ROMTOP;
-	. = CONFIG_X86_RESET_VECTOR;
 	.reset . : {
 		*(.reset);
 		. = 15;

src/cpu/x86/smm/smm_module_loader.c

@@ -209,6 +209,12 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size,
 	smm_stub_size = rmodule_memory_size(&smm_stub);
 	stub_entry_offset = rmodule_entry_offset(&smm_stub);
 
+	if (smm_stub_size > params->per_cpu_save_state_size) {
+		printk(BIOS_ERR, "SMM Module: SMM stub size larger than save state size\n");
+		printk(BIOS_ERR, "SMM Module: Staggered entry points will overlap stub\n");
+		return -1;
+	}
+
 	/* Assume the stub is always small enough to live within upper half of
 	 * SMRAM region after the save state space has been allocated. */
 	smm_stub_loc = &base[SMM_ENTRY_OFFSET];

src/cpu/x86/smm/smm_module_loaderv2.c

@@ -134,6 +134,12 @@ static int smm_create_map(uintptr_t smbase, unsigned int num_cpus,
 		return 0;
 	}
 
+	if (stub_size > ss_size) {
+		printk(BIOS_ERR, "%s: Save state larger than SMM stub size\n", __func__);
+		printk(BIOS_ERR, "    Decrease stub size or increase the size allocated for the save state\n");
+		return 0;
+	}
+
 	for (i = 0; i < num_cpus; i++) {
 		cpus[i].smbase = base;
 		cpus[i].entry = base + smm_entry_offset;
@@ -407,12 +413,14 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size,
 	 * for default handler, but for relocated handler it lives at the beginning
 	 * of SMRAM which is TSEG base
 	 */
-	size = params->num_concurrent_stacks * params->per_cpu_stack_size;
+	const size_t total_stack_size = params->num_concurrent_stacks *
-	stacks_top = smm_stub_place_stacks((char *)params->smram_start, size, params);
+		params->per_cpu_stack_size;
+	stacks_top = smm_stub_place_stacks((char *)params->smram_start, total_stack_size,
+					   params);
 	if (stacks_top == NULL) {
 		printk(BIOS_ERR, "%s: not enough space for stacks\n", __func__);
 		printk(BIOS_ERR, "%s: ....need -> %p : available -> %zx\n", __func__,
-			base, size);
+			base, total_stack_size);
 		return -1;
 	}
 	params->stack_top = stacks_top;
@@ -440,8 +448,8 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size,
 	stub_params->runtime.save_state_size = params->per_cpu_save_state_size;
 	stub_params->runtime.num_cpus = params->num_concurrent_stacks;
 
-	printk(BIOS_DEBUG, "%s: stack_end = 0x%x\n",
+	printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n",
-		__func__, stub_params->runtime.smbase);
+		__func__, stub_params->stack_top - total_stack_size);
 	printk(BIOS_DEBUG,
 		"%s: stack_top = 0x%x\n", __func__, stub_params->stack_top);
 	printk(BIOS_DEBUG, "%s: stack_size = 0x%x\n",

src/device/Kconfig

@@ -534,9 +534,20 @@ config PCI_ALLOW_BUS_MASTER
 
 if PCI_ALLOW_BUS_MASTER
 
+config PCI_SET_BUS_MASTER_PCI_BRIDGES
+	bool "PCI bridges"
+	default y
+	help
+	  Let coreboot configure bus mastering for PCI bridges. Enabling bus
+	  mastering for a PCI bridge also allows it to forward requests from
+	  downstream devices. Currently, payloads ignore this and only enable
+	  bus mastering for the downstream device. Hence, this option is needed
+	  for compatibility until payloads are fixed.
+
 config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
 	bool "Any devices"
 	default y
+	select PCI_SET_BUS_MASTER_PCI_BRIDGES
 	help
 	  Allow coreboot to enable PCI bus mastering for any device. The actual
 	  selection of devices depends on the various PCI drivers in coreboot.

src/device/pci_device.c

@@ -542,7 +542,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
 			dev->command |= PCI_COMMAND_MEMORY;
 		if (resource->flags & IORESOURCE_IO)
 			dev->command |= PCI_COMMAND_IO;
-		if (resource->flags & IORESOURCE_PCI_BRIDGE)
+		if (resource->flags & IORESOURCE_PCI_BRIDGE &&
+		    CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES))
 			dev->command |= PCI_COMMAND_MASTER;
 	}
 
@@ -953,13 +954,16 @@ static void set_pci_ops(struct device *dev)
 		if ((driver->vendor == dev->vendor) &&
 		    device_id_match(driver, dev->device)) {
 			dev->ops = (struct device_operations *)driver->ops;
-			printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
+			break;
-			       dev_path(dev), driver->vendor, driver->device,
-			       (driver->ops->scan_bus ? "bus " : ""));
-			return;
 		}
 	}
 
+	if (dev->ops) {
+		printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev),
+		       driver->vendor, driver->device, (driver->ops->scan_bus ? "bus " : ""));
+		return;
+	}
+
 	/* If I don't have a specific driver use the default operations. */
 	switch (dev->hdr_type & 0x7f) {	/* Header type */
 	case PCI_HEADER_TYPE_NORMAL:
@@ -1128,7 +1132,8 @@ struct device *pci_probe_dev(struct device *dev, struct bus *bus,
 	dev->class = class >> 8;
 
 	/* Architectural/System devices always need to be bus masters. */
-	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
+	if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM &&
+	    CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
 		dev->command |= PCI_COMMAND_MASTER;
 
 	/*

src/drivers/aspeed/common/ast_mode_corebootfb.c

@@ -2,6 +2,8 @@
 /*
  * Copied from Linux drivers/gpu/drm/ast/ast_mode.c
  */
+
+#include <console/console.h>
 #include <edid.h>
 #include <device/pci_def.h>
 

src/drivers/aspeed/common/ast_post.c

@@ -2,6 +2,7 @@
 
 #define COREBOOT_AST_FAILOVER_TIMEOUT	10000000
 
+#include <console/console.h>
 #include <delay.h>
 
 #include "ast_drv.h"

src/drivers/i2c/designware/dw_i2c.c

@@ -419,6 +419,15 @@ static int _dw_i2c_transfer(unsigned int bus, const struct i2c_msg *segments,
 	/* Read to clear INTR_STAT_STOP_DET */
 	read32(&regs->clear_stop_det_intr);
 
+	/* Check TX abort */
+	if (read32(&regs->raw_intr_stat) & INTR_STAT_TX_ABORT) {
+		printk(BIOS_ERR, "I2C TX abort detected (%08x)\n",
+		       read32(&regs->tx_abort_source));
+		/* clear INTR_STAT_TX_ABORT */
+		read32(&regs->clear_tx_abrt_intr);
+		goto out;
+	}
+
 	/* Wait for the bus to go idle */
 	if (dw_i2c_wait_for_bus_idle(regs)) {
 		printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus);
@@ -747,8 +756,8 @@ int dw_i2c_init(unsigned int bus, const struct dw_i2c_bus_config *bcfg)
 	write32(&regs->rx_thresh, 0);
 	write32(&regs->tx_thresh, 0);
 
-	/* Enable stop detection interrupt */
+	/* Enable stop detection and TX abort interrupt */
-	write32(&regs->intr_mask, INTR_STAT_STOP_DET);
+	write32(&regs->intr_mask, INTR_STAT_STOP_DET | INTR_STAT_TX_ABORT);
 
 	printk(BIOS_INFO, "DW I2C bus %u at %p (%u KHz)\n",
 	       bus, regs, speed / KHz);

src/drivers/i2c/designware/dw_i2c.h

@@ -17,7 +17,7 @@
 
 /*
  * Timing values are in units of clock period, with the clock speed
- * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_I2C_CLOCK_MHZ
+ * provided by the SOC in CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
  * Automatic configuration is done based on requested speed, but the
  * values may need tuned depending on the board and the number of
  * devices present on the bus.

src/drivers/i2c/rx6110sa/rx6110sa.c

@@ -198,7 +198,6 @@ static void rx6110sa_fill_ssdt(const struct device *dev)
 	/* Device */
 	acpigen_write_scope(scope);
 	acpigen_write_device(acpi_device_name(dev));
-	acpigen_write_name_string("_HID", RX6110SA_HID_NAME);
 	acpigen_write_name_string("_DDN", RX6110SA_HID_DESC);
 	acpigen_write_STA(acpi_device_status(dev));
 

src/drivers/i2c/rx6110sa/rx6110sa.h

@@ -4,7 +4,6 @@
 #define _I2C_RX6110SA_H_
 
 #define RX6110SA_ACPI_NAME		"ERX6"
-#define RX6110SA_HID_NAME		"RX6110SA"
 #define RX6110SA_HID_DESC		"Real Time Clock"
 
 /* Register layout */

src/drivers/i2c/tpm/tpm.c

@@ -424,11 +424,6 @@ static int tpm_tis_i2c_send(struct tpm_chip *chip, uint8_t *buf, size_t len)
 		if (burstcnt > (len-1-count))
 			burstcnt = len-1-count;
 
-#ifdef CONFIG_TPM_I2C_BURST_LIMITATION
-		if (burstcnt > CONFIG_TPM_I2C_BURST_LIMITATION)
-			burstcnt = CONFIG_TPM_I2C_BURST_LIMITATION;
-#endif /* CONFIG_TPM_I2C_BURST_LIMITATION */
-
 		if (iic_tpm_write(TPM_DATA_FIFO(chip->vendor.locality),
 						&(buf[count]), burstcnt) == 0)
 			count += burstcnt;

src/drivers/intel/fsp1_1/Makefile.inc

@@ -4,7 +4,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
 
 verstage-y += car.c
 verstage-y += fsp_util.c
-verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c
+verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
 
 bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
 bootblock-y += fsp_util.c

src/drivers/intel/fsp1_1/cache_as_ram.S

@@ -133,7 +133,7 @@ CAR_init_done:
 	jne	halt2
 
 	/* Setup bootloader stack */
-	movl	%edx, %esp
+	movl	$_ecar_stack, %esp
 
 	/*
 	 * ebp:  FSP_INFO_HEADER address

src/drivers/wifi/generic/acpi.c

@@ -53,7 +53,7 @@ static void emit_sar_acpi_structures(const struct device *dev)
 
 	/* Retrieve the sar limits data */
 	if (get_wifi_sar_limits(&sar_limits) < 0) {
-		printk(BIOS_ERR, "Error: failed from getting SAR limits!\n");
+		printk(BIOS_DEBUG, "failed from getting SAR limits!\n");
 		return;
 	}
 

src/ec/google/chromeec/ec.c

@@ -1624,6 +1624,53 @@ int google_chromeec_ap_reset(void)
 	return 0;
 }
 
+int google_chromeec_regulator_enable(uint32_t index, uint8_t enable)
+{
+	struct ec_params_regulator_enable params = {
+		.index = index,
+		.enable = enable,
+	};
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_REGULATOR_ENABLE,
+		.cmd_version = 0,
+		.cmd_data_in = &params,
+		.cmd_size_in = sizeof(params),
+		.cmd_data_out = NULL,
+		.cmd_size_out = 0,
+		.cmd_dev_index = 0,
+	};
+
+	if (google_chromeec_command(&cmd))
+		return -1;
+
+	return 0;
+}
+
+int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled)
+{
+
+	struct ec_params_regulator_is_enabled params = {
+		.index = index,
+	};
+	struct ec_response_regulator_is_enabled resp = {};
+	struct chromeec_command cmd = {
+		.cmd_code = EC_CMD_REGULATOR_IS_ENABLED,
+		.cmd_version = 0,
+		.cmd_data_in = &params,
+		.cmd_size_in = sizeof(params),
+		.cmd_data_out = &resp,
+		.cmd_size_out = sizeof(resp),
+		.cmd_dev_index = 0,
+	};
+
+	if (google_chromeec_command(&cmd))
+		return -1;
+
+	*enabled = resp.enabled;
+
+	return 0;
+}
+
 int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv,
 					  uint32_t max_mv)
 {

src/ec/google/chromeec/ec.h

@@ -353,8 +353,27 @@ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd);
  */
 int google_chromeec_ap_reset(void);
 
+/**
+ * Configure the regulator as enabled / disabled.
+ *
+ * @param index		Regulator ID
+ * @param enable	Set to enable / disable the regulator
+ * @return		0 on success, -1 on error
+ */
+int google_chromeec_regulator_enable(uint32_t index, uint8_t enable);
+
+/**
+ * Query if the regulator is enabled.
+ *
+ * @param index		Regulator ID
+ * @param *enabled	If successful, enabled indicates enable/disable status.
+ * @return		0 on success, -1 on error
+ */
+int google_chromeec_regulator_is_enabled(uint32_t index, uint8_t *enabled);
+
 /**
  * Set voltage for the voltage regulator within the range specified.
+ *
  * @param index		Regulator ID
  * @param min_mv	Minimum voltage
  * @param max_mv	Maximum voltage
@@ -365,6 +384,7 @@ int google_chromeec_regulator_set_voltage(uint32_t index, uint32_t min_mv,
 
 /**
  * Get the currently configured voltage for the voltage regulator.
+ *
  * @param index		Regulator ID
  * @param *voltage_mv	If successful, voltage_mv is filled with current voltage
  * @return		0 on success, -1 on error

src/ec/google/chromeec/ec_commands.h

@@ -1388,7 +1388,7 @@ enum ec_feature_code {
 	 */
 	EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37,
 	/*
-	 * Early Firmware Selection ver.2. Enabled by CONFIG_VBOOT_EFS2.
+	 * Early Firmware Selection ver.2. Enabled by VBOOT_EFS2 config option.
 	 * Note this is a RO feature. So, a query (EC_CMD_GET_FEATURES) should
 	 * be sent to RO to be precise.
 	 */

src/include/acpi/acpi.h

@@ -1077,6 +1077,7 @@ unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
 void __noreturn acpi_resume(void *wake_vec);
 void mainboard_suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
+int acpi_handoff_wakeup_s3(void);
 
 /* ACPI_Sn assignments are defined to always equal the sleep state numbers */
 enum {
@@ -1104,6 +1105,8 @@ static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
 }
 #endif
 
+uint8_t acpi_get_preferred_pm_profile(void);
+
 /* Returns ACPI_Sx values. */
 int acpi_get_sleep_type(void);
 
@@ -1122,24 +1125,16 @@ static inline int acpi_s3_resume_allowed(void)
 	return CONFIG(HAVE_ACPI_RESUME);
 }
 
-#if CONFIG(HAVE_ACPI_RESUME)
-
-#if ENV_ROMSTAGE_OR_BEFORE
 static inline int acpi_is_wakeup_s3(void)
 {
-	return (acpi_get_sleep_type() == ACPI_S3);
+	if (!acpi_s3_resume_allowed())
-}
+		return 0;
-#else
-int acpi_is_wakeup(void);
-int acpi_is_wakeup_s3(void);
-int acpi_is_wakeup_s4(void);
-#endif
 
-#else
+	if (ENV_ROMSTAGE_OR_BEFORE)
-static inline int acpi_is_wakeup(void) { return 0; }
+		return (acpi_get_sleep_type() == ACPI_S3);
-static inline int acpi_is_wakeup_s3(void) { return 0; }
+
-static inline int acpi_is_wakeup_s4(void) { return 0; }
+	return acpi_handoff_wakeup_s3();
-#endif
+}
 
 static inline uintptr_t acpi_align_current(uintptr_t current)
 {

src/include/device/dram/ddr2.h

@@ -47,35 +47,35 @@ union dimm_flags_ddr2_st {
 	 * We do not care how these bits are ordered */
 	struct {
 		/* Module can work at 5.00V */
-		unsigned operable_5_00V:1;
+		unsigned int operable_5_00V:1;
 		/* Module can work at 3.33V */
-		unsigned operable_3_33V:1;
+		unsigned int operable_3_33V:1;
 		/* Module can work at 2.50V */
-		unsigned operable_2_50V:1;
+		unsigned int operable_2_50V:1;
 		/* Module can work at 1.80V - All DIMMS must be 1.8V operable */
-		unsigned operable_1_80V:1;
+		unsigned int operable_1_80V:1;
 		/* Module can work at 1.50V */
-		unsigned operable_1_50V:1;
+		unsigned int operable_1_50V:1;
 		/* Module can work at 1.35V */
-		unsigned operable_1_35V:1;
+		unsigned int operable_1_35V:1;
 		/* Module can work at 1.20V */
-		unsigned operable_1_25V:1;
+		unsigned int operable_1_25V:1;
 		/* Has an 8-bit bus extension, meaning the DIMM supports ECC */
-		unsigned is_ecc:1;
+		unsigned int is_ecc:1;
 		/* Supports weak driver */
-		unsigned weak_driver:1;
+		unsigned int weak_driver:1;
 		/* Supports terminating at 50 Ohm */
-		unsigned terminate_50ohms:1;
+		unsigned int terminate_50ohms:1;
 		/* Partial Array Self Refresh */
-		unsigned pasr:1;
+		unsigned int pasr:1;
 		/* Supports burst length 8 */
-		unsigned bl8:1;
+		unsigned int bl8:1;
 		/* Supports burst length 4 */
-		unsigned bl4:1;
+		unsigned int bl4:1;
 		/* DIMM Package is stack */
-		unsigned stacked:1;
+		unsigned int stacked:1;
 		/* the assembly supports self refresh */
-		unsigned self_refresh:1;
+		unsigned int self_refresh:1;
 	};
 	unsigned int raw;
 };

src/include/device/pci_ids.h

@@ -453,24 +453,21 @@
 #define PCI_DEVICE_ID_AMD_CZ_USB3_0	0x7914
 #define PCI_DEVICE_ID_AMD_CZ_SMBUS	0x790B
 
-#define PCI_DEVICE_ID_AMD_FAM17H_GNB				0x15D0
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP		0x15D3
-#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP			0x15D3
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA		0x15DB
-#define PCI_DEVICE_ID_AMD_FAM17H_GPU				0x15D8
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB		0x15DC
-#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSA			0x15DB
-#define PCI_DEVICE_ID_AMD_FAM17H_PCIE_GPP_BUSB			0x15DC
-#define PCI_DEVICE_ID_AMD_FAM17H_HDA0				0x15DE
 #define PCI_DEVICE_ID_AMD_FAM17H_ACP				0x15E2
 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1				0x15E3
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0			0x15E0
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1			0x15E1
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0			0x15E5
-#define PCI_DEVICE_ID_AMD_FAM17H_DF0				0x15E8
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0			0x15E8
-#define PCI_DEVICE_ID_AMD_FAM17H_DF1				0x15E9
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1			0x15E9
-#define PCI_DEVICE_ID_AMD_FAM17H_DF2				0x15EA
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2			0x15EA
-#define PCI_DEVICE_ID_AMD_FAM17H_DF3				0x15EB
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF3			0x15EB
-#define PCI_DEVICE_ID_AMD_FAM17H_DF4				0x15EC
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4			0x15EC
-#define PCI_DEVICE_ID_AMD_FAM17H_DF5				0x15ED
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5			0x15ED
-#define PCI_DEVICE_ID_AMD_FAM17H_DF6				0x15EE
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6			0x15EE
 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0			0x7901
 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1			0x7904
 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0		0x7916
@@ -478,7 +475,10 @@
 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_SD			0x7906
 #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS				0x790B
 #define PCI_DEVICE_ID_AMD_FAM17H_LPC				0x790E
-#define PCI_DEVICE_ID_AMD_FAM17H_GBE				0x1458
+#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE			0x1458
+
+#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU			0x15D8
+#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0			0x15DE
 
 #define PCI_VENDOR_ID_VLSI		0x1004
 #define PCI_DEVICE_ID_VLSI_82C592	0x0005

src/include/rules.h

@@ -63,10 +63,11 @@
 
 /*
  * NOTE: "verstage" code may either run as a separate stage or linked into the
- * bootblock/romstage, depending on the setting of CONFIG_SEPARATE_VERSTAGE. The
+ * bootblock/romstage, depending on the setting of the VBOOT_SEPARATE_VERSTAGE
- * ENV_SEPARATE_VERSTAGE macro will only return true for "verstage" code when
+ * kconfig option. The ENV_SEPARATE_VERSTAGE macro will only return true for
- * CONFIG_SEPARATE_VERSTAGE=y, otherwise that code will have ENV_BOOTBLOCK or
+ * "verstage" code when CONFIG(VBOOT_SEPARATE_VERSTAGE) is true, otherwise that
- * ENV_ROMSTAGE set (depending on the CONFIG_VBOOT_STARTS_IN_... options).
+ * code will have ENV_BOOTBLOCK or ENV_ROMSTAGE set (depending on the
+ * "VBOOT_STARTS_IN_"... kconfig options).
  */
 #elif defined(__VERSTAGE__)
 #define ENV_DECOMPRESSOR 0

src/lib/asan.c

@@ -8,6 +8,7 @@
  *
  */
 
+#include <console/console.h>
 #include <symbols.h>
 #include <assert.h>
 #include <arch/symbols.h>

src/lib/gnat/i-c.ads

@@ -59,6 +59,9 @@ package Interfaces.C is
 
    type size_t is mod 2 ** System.Parameters.ptr_bits;
 
+   --  For convenience, also provide an uintptr_t type
+   type uintptr_t is mod 2 ** System.Parameters.ptr_bits;
+
    ----------------------------
    -- Characters and Strings --
    ----------------------------

src/lib/hardwaremain.c

@@ -444,7 +444,7 @@ void main(void)
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* Handoff sleep type from romstage. */
-	acpi_is_wakeup();
+	acpi_is_wakeup_s3();
 	threads_initialize();
 
 	/* Schedule the static boot state entries. */

src/lib/romstage_handoff.c

@@ -8,7 +8,7 @@
 
 struct romstage_handoff {
 	/* Indicate if the current boot is an S3 resume. If
-	 * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
+	 * CONFIG_RELOCATABLE_RAMSTAGE is enabled the chipset code is
 	 * responsible for initializing this variable. Otherwise, ramstage
 	 * will be re-loaded from cbfs (which can be slower since it lives
 	 * in flash). */

src/mainboard/asus/f2a85-m/buildOpts.c

@@ -51,6 +51,7 @@
 #define BLDCFG_FCH_GPP_LINK_CONFIG		PortA1B1C1D1
 #define BLDCFG_FCH_GPP_PORT0_PRESENT		TRUE
 #define BLDCFG_FCH_GPP_PORT1_PRESENT		TRUE
+#define BLDCFG_FCH_GPP_PORT2_PRESENT		CONFIG(BOARD_ASUS_F2A85_M_PRO)
 
 GPIO_CONTROL f2a85_m_gpio[] = {
 	{-1}

src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb

@@ -111,7 +111,9 @@ chip northbridge/amd/agesa/family15tn/root_complex
 				device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806])
 				device pci 15.0 on end # PCI bridge
 				device pci 15.1 on end # PCI bridge
-				device pci 15.2 on end # PCI bridge # Only present with the original boot firmware
+				# FIXME: serial console stops working when enabling resources
+				# for 15.2, and payloads hang
+				device pci 15.2 off end # PCI bridge
 			end	#chip southbridge/amd/hudson
 
 			device pci 18.0 on end

src/mainboard/clevo/cml-u/Kconfig.name

@@ -1,2 +1,4 @@
+comment "Comet Lake U"
+
 config BOARD_CLEVO_L140CU
-	bool "L140CU"
+	bool "L140CU / L141CU"

src/mainboard/clevo/kbl-u/Kconfig

@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_CLEVO_N130WU
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select EC_ACPI
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+#	select HAVE_CMOS_DEFAULT
+#	select HAVE_SMI_HANDLER
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_KABYLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config VBOOT
+	select VBOOT_NO_BOARD_SUPPORT
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+
+config MAINBOARD_DIR
+	string
+	default "clevo/kbl-u"
+
+config VARIANT_DIR
+	string
+	default "n13xwu" if BOARD_CLEVO_N130WU
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "N130WU" if BOARD_CLEVO_N130WU
+
+config CBFS_SIZE
+	hex
+	default 0x600000 if BOARD_CLEVO_N130WU
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd"	if VBOOT && !VBOOT_SLOTS_RW_A
+	# TODO
+#	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd"	if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
+#	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd"	if VBOOT_SLOTS_RW_AB
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VGA_BIOS_ID
+	string
+	default "8086,5917" if BOARD_CLEVO_N130WU
+
+config PXE_ROM_ID
+	string
+	default "10ec,8168"
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config POST_DEVICE
+	bool
+	default n
+
+config CONSOLE_POST
+	bool
+	default y
+
+config LINEAR_FRAMEBUFFER_MAX_WIDTH
+	int
+	default 1920
+
+config LINEAR_FRAMEBUFFER_MAX_HEIGHT
+	int
+	default 1080
+
+endif

src/mainboard/clevo/kbl-u/Kconfig.name

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+comment "Kaby Lake U"
+
+config BOARD_CLEVO_N130WU
+	bool "N130WU / N131WU"

src/mainboard/clevo/kbl-u/Makefile.inc

@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads

src/mainboard/clevo/kbl-u/acpi/superio.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>

src/mainboard/clevo/kbl-u/board_info.txt

@@ -0,0 +1,7 @@
+Vendor name: Clevo
+Category: laptop
+Release year: 2018
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/clevo/kbl-u/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_configure_gpios();
+}

src/mainboard/clevo/kbl-u/dsdt.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}

src/mainboard/clevo/kbl-u/include/mainboard/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_gpios(void);
+
+#endif

src/mainboard/clevo/kbl-u/ramstage.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+/*
+ * TODO:
+ * - Add kill switches for WLAN, BT, LTE, CCD
+ * - Add support for WoL (LAN, WLAN)
+ * - Make M.2 port configurable (SATA <> PCIe)
+ *   - Make SATA DevSlp configurable
+ * - Make TBT port configurable (TBT <> DisplayPort)
+ */
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+	mainboard_configure_gpios();
+}

src/mainboard/clevo/kbl-u/romstage.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+	const u16 RcompResistor[3] = {121, 81, 100};
+	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+	const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	struct spd_block blk = {
+		.addr_map = {0x50, 0x52},
+	};
+
+	mem_cfg = &mupd->FspmConfig;
+
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}

src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt

@@ -0,0 +1 @@
+Board name: N130WU / N131WU

src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb

@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	register "gpu_pp_up_delay_ms"		  = "200"	# T3
+	register "gpu_pp_down_delay_ms"		  = "  0"	# T10
+	register "gpu_pp_cycle_delay_ms"	  = "500"	# T12
+	register "gpu_pp_backlight_on_delay_ms"	  = " 50"	# T7
+	register "gpu_pp_backlight_off_delay_ms"  = "  0"	# T9
+
+	register "gpu_pch_backlight_pwm_hz"	  = "200"
+
+	# IGD Displays
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+	# FSP Configuration
+	register "SkipExtGfxScan" = "1"
+	register "SaGv" = "SaGv_Enabled"
+	register "eist_enable" = "1"
+
+	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
+	register "PmConfigSlpS4MinAssert" = "1"		# 1s
+	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
+	register "PmConfigSlpAMinAssert" = "3"		# 2s
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 30,
+	}"
+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		subsystemid 0x1558 0x1313 inherit
+		device pci 00.0 on	end # Host Bridge
+		device pci 02.0 on	end # Integrated Graphics Device
+		device pci 04.0 on	end # SA thermal subsystem
+		device pci 05.0 off	end # Imaging Unit
+		device pci 08.0 on	end # Gaussian Mixture Model
+		device pci 13.0 off	end # Sensor Hub
+		device pci 14.0 on	    # USB xHCI
+			register "SsicPortEnable" = "0"
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A, right
+			register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)"	# 3G / LTE
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C, right
+			register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
+			register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"	# Bluetooth
+			register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Type-A, left
+			register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C, right
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# 4G
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type C, right
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A, left
+		end
+		device pci 14.1 off	end # USB xDCI (OTG)
+		device pci 14.2 on	end # Thermal Subsystem
+		device pci 14.3 off	end # Camera
+		device pci 15.0 off	end # I2C0
+		device pci 15.1 off	end # I2C1
+		device pci 15.2 off	end # I2C2
+		device pci 15.3 off	end # I2C3
+		device pci 16.0 on	    # Management Engine Interface 1
+			register "HeciEnabled" = "1"
+		end
+		device pci 16.1 off	end # Management Engine Interface 2
+		device pci 16.2 off	end # Management Engine IDE-R
+		device pci 16.3 off	end # Management Engine KT Redirection
+		device pci 16.4 off	end # Management Engine Interface 3
+		device pci 17.0	on	    # SATA
+			register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
+			register "SataSalpSupport" = "0"
+			# Ports
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[2]" = "1"
+			register "SataPortsDevSlp[2]" = "1"
+		end
+		device pci 19.0 on	end # UART 2
+		device pci 19.1 off	end # I2C5
+		device pci 19.2 off	end # I2C4
+		device pci 1c.0 on	    # PCI Express Port 1
+			device pci 00.0 on end # x4 TBT
+			register "PcieRpEnable[0]" = "1"
+			register "PcieRpClkReqSupport[0]" = "1"
+			register "PcieRpClkReqNumber[0]" = "4"
+			register "PcieRpClkSrcNumber[0]" = "4"
+			register "PcieRpHotPlug[0]" = "1"
+			register "PcieRpLtrEnable[0]" = "1"
+			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
+		end
+		device pci 1c.1 off	end # PCI Express Port 2
+		device pci 1c.2 off	end # PCI Express Port 3
+		device pci 1c.3 off	end # PCI Express Port 4
+		device pci 1c.4 on	    # PCI Express Port 5
+			device pci 00.0 on end # x1 LAN
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpClkReqSupport[4]" = "1"
+			register "PcieRpClkReqNumber[4]" = "3"
+			register "PcieRpClkSrcNumber[4]" = "3"
+			register "PcieRpLtrEnable[4]" = "1"
+		end
+		device pci 1c.5 on	    # PCI Express Port 6
+			device pci 00.0 on end # x1 WLAN
+			register "PcieRpEnable[5]" = "1"
+			register "PcieRpClkReqSupport[5]" = "1"
+			register "PcieRpClkReqNumber[5]" = "2"
+			register "PcieRpClkSrcNumber[5]" = "2"
+			register "PcieRpLtrEnable[5]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+		end
+		device pci 1c.6 off	end # PCI Express Port 7
+		device pci 1c.7 off	end # PCI Express Port 8
+		device pci 1d.0 on	    # PCI Express Port 9
+			device pci 00.0 on end # x4 M.2/M (J_SSD1)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpClkReqSupport[8]" = "1"
+			register "PcieRpClkReqNumber[8]" = "5"
+			register "PcieRpClkSrcNumber[8]" = "5"
+			register "PcieRpLtrEnable[8]" = "1"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+		end
+		device pci 1d.1 off	end # PCI Express Port 10
+		device pci 1d.2 off	end # PCI Express Port 11
+		device pci 1d.3 off	end # PCI Express Port 12
+		device pci 1e.0 off	end # UART 0
+		device pci 1e.1	off	end # UART 1
+		device pci 1e.2 off	end # GSPI 0
+		device pci 1e.3 off	end # GSPI 1
+		device pci 1e.4 off	end # eMMC
+		device pci 1e.5 off	end # SDIO
+		device pci 1e.6 off	end # SDXC
+		device pci 1f.0 on	    # LPC Interface
+			register "gen1_dec" = "0x000c0681"
+			register "gen2_dec" = "0x000c1641"
+			register "gen3_dec" = "0x000c0081"
+			register "gen4_dec" = "0x00040069"
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device pci 1f.1 hidden	end # P2SB
+		device pci 1f.2 on	    # Power Management Controller
+			register "gpe0_dw0" = "GPP_C"
+			register "gpe0_dw1" = "GPP_D"
+			register "gpe0_dw2" = "GPP_E"
+		end
+		device pci 1f.3 on	end # Intel HDA
+		device pci 1f.4 on	end # SMBus
+		device pci 1f.5 on	end # PCH SPI
+		device pci 1f.6 off	end # GbE
+		device pci 1f.7 off	end # Trace Hub
+	end
+end

src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd

@@ -0,0 +1,32 @@
+FLASH 8M {
+	SI_ALL@0x0 0x200000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x1ff000
+	}
+	SI_BIOS@0x200000 0x600000 {
+		MISC_RW@0x0 0x2d000 {
+			UNIFIED_MRC_CACHE@0x0 0x21000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+				RW_VAR_MRC_CACHE@0x20000 0x1000
+			}
+			RW_SHARED@0x21000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD(PRESERVE)@0x25000 0x2000
+			RW_NVRAM(PRESERVE)@0x27000 0x5000
+			FPF_STATUS@0x2c000 0x1000
+		}
+		WP_RO@0x2d000 0x5d3000 {
+			FMAP@0x0 0x800
+			RO_VPD(PRESERVE)@0x800 0x4000
+			RO_SECTION@0x4800 0x5ce800 {
+				RO_FRID@0x0 0x40
+				RO_FRID_PAD@0x40 0x7c0
+				GBB@0x800 0x40000
+				COREBOOT(CBFS)@0x40800 0x58e000
+			}
+		}
+	}
+}

src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads

@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (eDP,
+      DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      others => Disabled);
+
+end GMA.Mainboard;

src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c

@@ -0,0 +1,503 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	// RCIN#
+	_PAD_CFG_STRUCT(GPP_A0,		0x44000502,	0x0),
+
+	// LAD0
+	_PAD_CFG_STRUCT(GPP_A1,		0x44000402,	0x0),
+
+	// LAD1
+	_PAD_CFG_STRUCT(GPP_A2,		0x44000402,	0x0),
+
+	// LAD2
+	_PAD_CFG_STRUCT(GPP_A3,		0x44000402,	0x0),
+
+	// LAD3
+	_PAD_CFG_STRUCT(GPP_A4,		0x44000402,	0x0),
+
+	// LFRAME#
+	_PAD_CFG_STRUCT(GPP_A5,		0x44000600,	0x0),
+
+	// SERIRQ
+	_PAD_CFG_STRUCT(GPP_A6,		0x44000402,	0x0),
+
+	// PIRQA#
+	_PAD_CFG_STRUCT(GPP_A7,		0x44000102,	0x0),
+
+	// CLKRUN#
+	_PAD_CFG_STRUCT(GPP_A8,		0x44000700,	0x0),
+
+	// CLKOUT_LPC0
+	_PAD_CFG_STRUCT(GPP_A9,		0x44000600,	0x0),
+
+	// CLKOUT_LPC1
+	_PAD_CFG_STRUCT(GPP_A10,	0x44000600,	0x1000),
+
+	// PME#
+	_PAD_CFG_STRUCT(GPP_A11,	0x44000200,	0x0),
+
+	// BM_BUSY#
+	_PAD_CFG_STRUCT(GPP_A12,	0x44000200,	0x0),
+
+	// SUSWARN#/SUSPWRDNACK
+	_PAD_CFG_STRUCT(GPP_A13,	0x44000200,	0x0),
+
+	// SUS_STAT#/ESPI_RESET#
+	_PAD_CFG_STRUCT(GPP_A14,	0x44000600,	0x0),
+
+	// SUS_ACK#
+	_PAD_CFG_STRUCT(GPP_A15,	0x44000502,	0x0),
+
+	// SD_1P8_SEL
+	_PAD_CFG_STRUCT(GPP_A16,	0x44000200,	0x0),
+
+	// SD_PWR_EN#
+	_PAD_CFG_STRUCT(GPP_A17,	0x44000200,	0x0),
+
+	// ISH_GP0
+	_PAD_CFG_STRUCT(GPP_A18,	0x44000201,	0x0),
+
+	// ISH_GP1
+	_PAD_CFG_STRUCT(GPP_A19,	0x44000603,	0x0),
+
+	// ISH_GP2
+	_PAD_CFG_STRUCT(GPP_A20,	0x44000200,	0x0),
+
+	// ISH_GP3
+	_PAD_CFG_STRUCT(GPP_A21,	0x84000200,	0x1000),
+
+	// ISH_GP4
+	_PAD_CFG_STRUCT(GPP_A22,	0x4000200,	0x0),
+
+	// ISH_GP5
+	_PAD_CFG_STRUCT(GPP_A23,	0x4000200,	0x0),
+
+	// CORE_VID0
+	_PAD_CFG_STRUCT(GPP_B0,		0x44000700,	0x0),
+
+	// CORE_VID1
+	_PAD_CFG_STRUCT(GPP_B1,		0x44000700,	0x0),
+
+	// VRALERT#
+	_PAD_CFG_STRUCT(GPP_B2,		0x44000200,	0x0),
+
+	// CPU_GP2
+	_PAD_CFG_STRUCT(GPP_B3,		0x44000200,	0x0),
+
+	// CPU_GP3
+	_PAD_CFG_STRUCT(GPP_B4,		0x44000200,	0x0),
+
+	// SRCCLKREQ0#
+	_PAD_CFG_STRUCT(GPP_B5,		0x44000200,	0x0),
+
+	// SRCCLKREQ1#
+	_PAD_CFG_STRUCT(GPP_B6,		0x44000200,	0x0),
+
+	// SRCCLKREQ2#
+	_PAD_CFG_STRUCT(GPP_B7,		0x44000700,	0x0),
+
+	// SRCCLKREQ3#
+	_PAD_CFG_STRUCT(GPP_B8,		0x44000700,	0x0),
+
+	// SRCCLKREQ4#
+	_PAD_CFG_STRUCT(GPP_B9,		0x44000702,	0x0),
+
+	// SRCCLKREQ5#
+	_PAD_CFG_STRUCT(GPP_B10,	0x44000702,	0x0),
+
+	// EXT_PWR_GATE#
+	_PAD_CFG_STRUCT(GPP_B11,	0x44000700,	0x0),
+
+	// SLP_S0#
+	_PAD_CFG_STRUCT(GPP_B12,	0x44000200,	0x0),
+
+	// PLTRST#
+	_PAD_CFG_STRUCT(GPP_B13,	0x44000700,	0x0),
+
+	// SPKR
+	_PAD_CFG_STRUCT(GPP_B14,	0x44000600,	0x1000),
+
+	// GSPI0_CS#
+	_PAD_CFG_STRUCT(GPP_B15,	0x44000200,	0x0),
+
+	// GSPI0_CLK
+	_PAD_CFG_STRUCT(GPP_B16,	0x44000200,	0x0),
+
+	// GSPI0_MISO
+	_PAD_CFG_STRUCT(GPP_B17,	0x44000200,	0x0),
+
+	// GSPI0_MOSI
+	_PAD_CFG_STRUCT(GPP_B18,	0x44000600,	0x3000),
+
+	// GSPI1_CS#
+	_PAD_CFG_STRUCT(GPP_B19,	0x44000200,	0x0),
+
+	// GSPI1_CLK
+	_PAD_CFG_STRUCT(GPP_B20,	0x44000200,	0x0),
+
+	// GSPI1_MISO
+	_PAD_CFG_STRUCT(GPP_B21,	0x44000200,	0x0),
+
+	// GSPI1_MOSI
+	_PAD_CFG_STRUCT(GPP_B22,	0x44000700,	0x1000),
+
+	// SML1ALERT#/PCHHOT#
+	_PAD_CFG_STRUCT(GPP_B23,	0x44000200,	0x0),
+
+	// SMBCLK
+	_PAD_CFG_STRUCT(GPP_C0,		0x44000702,	0x0),
+
+	// SMBDATA
+	_PAD_CFG_STRUCT(GPP_C1,		0x44000702,	0x1000),
+
+	// SMBALERT#
+	_PAD_CFG_STRUCT(GPP_C2,		0x44000201,	0x1000),
+
+	// SML0CLK
+	_PAD_CFG_STRUCT(GPP_C3,		0x44000200,	0x0),
+
+	// SML0DATA
+	_PAD_CFG_STRUCT(GPP_C4,		0x44000200,	0x0),
+
+	// SML0ALERT#
+	_PAD_CFG_STRUCT(GPP_C5,		0x44000200,	0x0),
+
+	// SML1CLK
+//	_PAD_CFG_STRUCT(GPP_C6,		0xffffffff,	0xffffff00),
+
+	// SML1DATA
+//	_PAD_CFG_STRUCT(GPP_C7,		0xffffffff,	0xffffff00),
+
+	// UART0_RXD
+	_PAD_CFG_STRUCT(GPP_C8,		0x44000700,	0x0),
+
+	// UART0_TXD
+	_PAD_CFG_STRUCT(GPP_C9,		0x44000700,	0x0),
+
+	// UART0_RTS#
+	_PAD_CFG_STRUCT(GPP_C10,	0x44000700,	0x0),
+
+	// UART0_CTS#
+	_PAD_CFG_STRUCT(GPP_C11,	0x44000700,	0x0),
+
+	// UART1_RXD
+	_PAD_CFG_STRUCT(GPP_C12,	0x44000702,	0x0),
+
+	// UART1_TXD
+	_PAD_CFG_STRUCT(GPP_C13,	0x82880102,	0x0),
+
+	// UART1_RTS#
+	_PAD_CFG_STRUCT(GPP_C14,	0x44000700,	0x0),
+
+	// UART1_CTS#
+	_PAD_CFG_STRUCT(GPP_C15,	0x44000700,	0x0),
+
+	// I2C0_SDA
+	_PAD_CFG_STRUCT(GPP_C16,	0x44000200,	0x0),
+
+	// I2C0_SCL
+	_PAD_CFG_STRUCT(GPP_C17,	0x44000200,	0x0),
+
+	// I2C1_SDA
+	_PAD_CFG_STRUCT(GPP_C18,	0x44000200,	0x0),
+
+	// I2C1_SCL
+	_PAD_CFG_STRUCT(GPP_C19,	0x40880102,	0x0),
+
+	// UART2_RXD
+	_PAD_CFG_STRUCT(GPP_C20,	0x44000702,	0x0),
+
+	// UART2_TXD
+	_PAD_CFG_STRUCT(GPP_C21,	0x44000700,	0x0),
+
+	// UART2_RTS#
+	_PAD_CFG_STRUCT(GPP_C22,	0x44000700,	0x0),
+
+	// UART2_CTS#
+	_PAD_CFG_STRUCT(GPP_C23,	0x44000700,	0x0),
+
+	// SPI1_CS#
+	_PAD_CFG_STRUCT(GPP_D0,		0x44000200,	0x0),
+
+	// SPI1_CLK
+	_PAD_CFG_STRUCT(GPP_D1,		0x44000200,	0x0),
+
+	// SPI1_MISO
+	_PAD_CFG_STRUCT(GPP_D2,		0x44000200,	0x0),
+
+	// SPI1_MOSI
+	_PAD_CFG_STRUCT(GPP_D3,		0x44000200,	0x0),
+
+	// FLASHTRIG
+	_PAD_CFG_STRUCT(GPP_D4,		0x44000200,	0x0),
+
+	// ISH_I2C0_SDA
+	_PAD_CFG_STRUCT(GPP_D5,		0x44000700,	0x0),
+
+	// ISH_I2C0_SCL
+	_PAD_CFG_STRUCT(GPP_D6,		0x44000700,	0x0),
+
+	// ISH_I2C1_SDA
+	_PAD_CFG_STRUCT(GPP_D7,		0x44000700,	0x0),
+
+	// ISH_I2C1_SCL
+	_PAD_CFG_STRUCT(GPP_D8,		0x44000201,	0x0),
+
+	// GPIO
+	_PAD_CFG_STRUCT(GPP_D9,		0x44000200,	0x0),
+
+	// GPIO
+	_PAD_CFG_STRUCT(GPP_D10,	0x44000200,	0x0),
+
+	// GPIO
+	_PAD_CFG_STRUCT(GPP_D11,	0x44000200,	0x0),
+
+	// GPIO
+	_PAD_CFG_STRUCT(GPP_D12,	0x44000200,	0x0),
+
+	// ISH_UART0_RXD
+	_PAD_CFG_STRUCT(GPP_D13,	0x44000200,	0x0),
+
+	// ISH_UART0_TXD
+	_PAD_CFG_STRUCT(GPP_D14,	0x44000200,	0x0),
+
+	// ISH_UART0_RTS#
+	_PAD_CFG_STRUCT(GPP_D15,	0x44000700,	0x0),
+
+	// ISH_UART0_CTS#
+	_PAD_CFG_STRUCT(GPP_D16,	0x44000700,	0x0),
+
+	// DMIC_CLK1
+	_PAD_CFG_STRUCT(GPP_D17,	0x44000700,	0x0),
+
+	// DMIC_DATA1
+	_PAD_CFG_STRUCT(GPP_D18,	0x44000700,	0x0),
+
+	// DMIC_CLK0
+	_PAD_CFG_STRUCT(GPP_D19,	0x44000700,	0x0),
+
+	// DMIC_DATA0
+	_PAD_CFG_STRUCT(GPP_D20,	0x44000700,	0x0),
+
+	// SPI1_IO2
+	_PAD_CFG_STRUCT(GPP_D21,	0x44000102,	0x0),
+
+	// SPI1_IO3
+	_PAD_CFG_STRUCT(GPP_D22,	0x44000700,	0x0),
+
+	// I2S_MCLK
+	_PAD_CFG_STRUCT(GPP_D23,	0x44000700,	0x0),
+
+	// SATAXPCIE0/SATAGP0
+	_PAD_CFG_STRUCT(GPP_E0,		0x42100100,	0x1000),
+
+	// SATAXPCIE1/SATAGP1
+	_PAD_CFG_STRUCT(GPP_E1,		0x44000702,	0x0),
+
+	// SATAXPCIE2/SATAGP2
+	_PAD_CFG_STRUCT(GPP_E2,		0x44000502,	0x0),
+
+	// CPU_GP0
+	_PAD_CFG_STRUCT(GPP_E3,		0x40000000,	0x0),
+
+	// DEVSLP0
+	_PAD_CFG_STRUCT(GPP_E4,		0x4000700,	0x0),
+
+	// DEVSLP1
+	_PAD_CFG_STRUCT(GPP_E5,		0x4000700,	0x0),
+
+	// DEVSLP2
+	_PAD_CFG_STRUCT(GPP_E6,		0x44000200,	0x0),
+
+	// CPU_GP1
+	_PAD_CFG_STRUCT(GPP_E7,		0x44000100,	0x0),
+
+	// SATALED#
+	_PAD_CFG_STRUCT(GPP_E8,		0x44000700,	0x0),
+
+	// USB2_OC0#
+	_PAD_CFG_STRUCT(GPP_E9,		0x44000200,	0x0),
+
+	// USB2_OC1#
+	_PAD_CFG_STRUCT(GPP_E10,	0x44000200,	0x0),
+
+	// USB2_OC2#
+	_PAD_CFG_STRUCT(GPP_E11,	0x44000200,	0x0),
+
+	// USB2_OC3#
+	_PAD_CFG_STRUCT(GPP_E12,	0x44000200,	0x0),
+
+	// DDPB_HPD0
+	_PAD_CFG_STRUCT(GPP_E13,	0x44000700,	0x0),
+
+	// DDPC_HPD1
+	_PAD_CFG_STRUCT(GPP_E14,	0x44000700,	0x0),
+
+	// DDPD_HPD2
+	_PAD_CFG_STRUCT(GPP_E15,	0x42840102,	0x0),
+
+	// DDPE_HPD3
+	_PAD_CFG_STRUCT(GPP_E16,	0x80880102,	0x0),
+
+	// EDP_HPD
+	_PAD_CFG_STRUCT(GPP_E17,	0x44000702,	0x0),
+
+	// DDPB_CTRLCLK
+	_PAD_CFG_STRUCT(GPP_E18,	0x44000700,	0x0),
+
+	// DDPB_CTRLDATA
+	_PAD_CFG_STRUCT(GPP_E19,	0x44000700,	0x1000),
+
+	// DDPC_CTRLCLK
+	_PAD_CFG_STRUCT(GPP_E20,	0x44000702,	0x0),
+
+	// DDPC_CTRLDATA
+	_PAD_CFG_STRUCT(GPP_E21,	0x44000702,	0x1000),
+
+	// DDPD_CTRLCLK
+	_PAD_CFG_STRUCT(GPP_E22,	0x40100000,	0x0),
+
+	// DDPD_CTRLDATA
+	_PAD_CFG_STRUCT(GPP_E23,	0x44000201,	0x1000),
+
+	// BATLOW#
+	_PAD_CFG_STRUCT(GPD0,		0x4000702,	0x0),
+
+	// LANPHYPC
+	_PAD_CFG_STRUCT(GPD1,		0x4000700,	0x0),
+
+	// LAN_WAKE#
+	_PAD_CFG_STRUCT(GPD2,		0x880502,	0x0),
+
+	// PWRBTN#
+	_PAD_CFG_STRUCT(GPD3,		0x4000702,	0x3000),
+
+	// SLP_S3#
+	_PAD_CFG_STRUCT(GPD4,		0x4000700,	0x0),
+
+	// SLP_S4#
+	_PAD_CFG_STRUCT(GPD5,		0x4000700,	0x0),
+
+	// SLP_A#
+	_PAD_CFG_STRUCT(GPD6,		0x4000700,	0x0),
+
+	// RSVD
+	_PAD_CFG_STRUCT(GPD7,		0x4000301,	0x0),
+
+	// SUSCLK
+	_PAD_CFG_STRUCT(GPD8,		0x4000700,	0x0),
+
+	// SLP_WLAN#
+	_PAD_CFG_STRUCT(GPD9,		0x4000700,	0x0),
+
+	// SLP_S5#
+	_PAD_CFG_STRUCT(GPD10,		0x4000700,	0x0),
+
+	// LANPHYPC
+	_PAD_CFG_STRUCT(GPD11,		0x4000500,	0x0),
+
+	// I2S2_SCLK
+	_PAD_CFG_STRUCT(GPP_F0,		0x44000702,	0x0),
+
+	// I2S2_SFRM
+	_PAD_CFG_STRUCT(GPP_F1,		0x44000702,	0x0),
+
+	// I2S2_TXD
+	_PAD_CFG_STRUCT(GPP_F2,		0x44000700,	0x0),
+
+	// I2S2_RXD
+	_PAD_CFG_STRUCT(GPP_F3,		0x44000702,	0x0),
+
+	// I2C2_SDA
+	_PAD_CFG_STRUCT(GPP_F4,		0x44000702,	0x2000000),
+
+	// I2C2_SCL
+	_PAD_CFG_STRUCT(GPP_F5,		0x44000702,	0x2000000),
+
+	// I2C3_SDA
+	_PAD_CFG_STRUCT(GPP_F6,		0x44000702,	0x2000000),
+
+	// I2C3_SCL
+	_PAD_CFG_STRUCT(GPP_F7,		0x44000702,	0x2000000),
+
+	// I2C4_SDA
+	_PAD_CFG_STRUCT(GPP_F8,		0x44000702,	0x2000000),
+
+	// I2C4_SCL
+	_PAD_CFG_STRUCT(GPP_F9,		0x44000702,	0x2000000),
+
+	// I2C5_SDA/ISH_I2C2_SDA
+	_PAD_CFG_STRUCT(GPP_F10,	0x44000b02,	0x2000000),
+
+	// I2C5_SCL/ISH_I2C2_SCL
+	_PAD_CFG_STRUCT(GPP_F11,	0x44000b02,	0x2000000),
+
+	// EMMC_CMD
+	_PAD_CFG_STRUCT(GPP_F12,	0x44000702,	0x0),
+
+	// EMMC_DATA0
+	_PAD_CFG_STRUCT(GPP_F13,	0x44000702,	0x0),
+
+	// EMMC_DATA1
+	_PAD_CFG_STRUCT(GPP_F14,	0x44000702,	0x0),
+
+	// EMMC_DATA2
+	_PAD_CFG_STRUCT(GPP_F15,	0x44000702,	0x0),
+
+	// EMMC_DATA3
+	_PAD_CFG_STRUCT(GPP_F16,	0x44000702,	0x0),
+
+	// EMMC_DATA4
+	_PAD_CFG_STRUCT(GPP_F17,	0x44000702,	0x0),
+
+	// EMMC_DATA5
+	_PAD_CFG_STRUCT(GPP_F18,	0x44000702,	0x0),
+
+	// EMMC_DATA6
+	_PAD_CFG_STRUCT(GPP_F19,	0x44000702,	0x0),
+
+	// EMMC_DATA7
+	_PAD_CFG_STRUCT(GPP_F20,	0x44000702,	0x0),
+
+	// EMMC_RCLK
+	_PAD_CFG_STRUCT(GPP_F21,	0x44000702,	0x0),
+
+	// EMMC_CLK
+	_PAD_CFG_STRUCT(GPP_F22,	0x44000700,	0x0),
+
+	// GPIO
+	_PAD_CFG_STRUCT(GPP_F23,	0x40100100,	0x0),
+
+	// SD_CMD
+	_PAD_CFG_STRUCT(GPP_G0,		0x44000700,	0x0),
+
+	// SD_DATA0
+	_PAD_CFG_STRUCT(GPP_G1,		0x44000102,	0x0),
+
+	// SD_DATA1
+	_PAD_CFG_STRUCT(GPP_G2,		0x44000700,	0x0),
+
+	// SD_DATA2
+	_PAD_CFG_STRUCT(GPP_G3,		0x44000700,	0x0),
+
+	// SD_DATA3
+	_PAD_CFG_STRUCT(GPP_G4,		0x44000700,	0x0),
+
+	// SD_CD#
+	_PAD_CFG_STRUCT(GPP_G5,		0x44000702,	0x0),
+
+	// SD_CLK
+	_PAD_CFG_STRUCT(GPP_G6,		0x44000700,	0x0),
+
+	// SD_WP
+	_PAD_CFG_STRUCT(GPP_G7,		0x44000702,	0x0)
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	// UART2_RXD
+	_PAD_CFG_STRUCT(GPP_C20,	0x44000702,	0x0),
+
+	// UART2_TXD
+	_PAD_CFG_STRUCT(GPP_C21,	0x44000700,	0x0)
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC269VC */
+	0x10ec0269,
+	0x15581314,
+	11,
+	AZALIA_SUBVENDOR(0, 0x15581314),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170120),
+	AZALIA_PIN_CFG(0, 0x15, 0x02211010),
+	AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+	/* Intel iGPU HDMI */
+	0x8086280b,
+	0x80860101,
+	4,
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x5, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x6, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x7, 0x18560010)
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/emulation/qemu-q35/chromeos.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <boot/coreboot_tables.h>
+#include <console/console.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include "../qemu-i440fx/fw_cfg.h"
 

src/mainboard/google/asurada/Makefile.inc

@@ -11,6 +11,7 @@ verstage-y += reset.c
 romstage-y += memlayout.ld
 romstage-y += boardid.c
 romstage-y += chromeos.c
+romstage-y += regulator.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
 
@@ -19,3 +20,4 @@ ramstage-y += boardid.c
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += reset.c
+ramstage-y += regulator.c

src/mainboard/google/asurada/mainboard.c

@@ -5,6 +5,7 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <soc/gpio.h>
+#include <soc/regulator.h>
 #include <soc/usb.h>
 
 #include "gpio.h"
@@ -14,7 +15,15 @@
 #define MSDC0_DRV_MASK	0x3fffffff
 #define MSDC1_DRV_MASK	0x3ffff000
 #define MSDC0_DRV_VALUE	0x24924924
-#define MSDC1_DRV_VALUE	0x24924000
+#define MSDC1_DRV_VALUE	0x1b6db000
+
+#define MSDC1_GPIO_MODE0_BASE	0x10005360
+#define MSDC1_GPIO_MODE0_MASK	0x77777000
+#define MSDC1_GPIO_MODE0_VALUE	0x11111000
+
+#define MSDC1_GPIO_MODE1_BASE	0x10005370
+#define MSDC1_GPIO_MODE1_MASK	0x7
+#define MSDC1_GPIO_MODE1_VALUE	0x1
 
 static void register_reset_to_bl31(void)
 {
@@ -57,6 +66,9 @@ static void configure_emmc(void)
 static void configure_sdcard(void)
 {
 	void *gpio_base = (void *)IOCFG_RM_BASE;
+	void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE;
+	void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE;
+	uint8_t enable = 1;
 	int i;
 
 	const gpio_t sdcard_pu_pin[] = {
@@ -75,8 +87,17 @@ static void configure_sdcard(void)
 	for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++)
 		gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
 
-	/* set sdcard cmd/dat/clk pins driving to 10mA */
+	/* set sdcard cmd/dat/clk pins driving to 8mA */
 	clrsetbits32(gpio_base, MSDC1_DRV_MASK, MSDC1_DRV_VALUE);
+
+	/* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */
+	clrsetbits32(gpio_mode0_base, MSDC1_GPIO_MODE0_MASK, MSDC1_GPIO_MODE0_VALUE);
+
+	/* set sdcard dat1 pin to msdc1 mode */
+	clrsetbits32(gpio_mode1_base, MSDC1_GPIO_MODE1_MASK, MSDC1_GPIO_MODE1_VALUE);
+
+	mainboard_enable_regulator(MTK_REGULATOR_VCC, enable);
+	mainboard_enable_regulator(MTK_REGULATOR_VCCQ, enable);
 }
 
 static void mainboard_init(struct device *dev)

src/mainboard/google/asurada/regulator.c

@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/mt6359p.h>
+#include <soc/mt6360.h>
+#include <soc/regulator.h>
+
+static int get_mt6360_regulator_id(enum mtk_regulator regulator)
+{
+	switch (regulator) {
+	case MTK_REGULATOR_VDD2:
+		return MT6360_BUCK1;
+	case MTK_REGULATOR_VDDQ:
+		return MT6360_LDO7;
+	case MTK_REGULATOR_VMDDR:
+		return MT6360_LDO6;
+	case MTK_REGULATOR_VCC:
+		return MT6360_LDO5;
+	case MTK_REGULATOR_VCCQ:
+		return MT6360_LDO3;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+static int get_mt6359p_regulator_id(enum mtk_regulator regulator)
+{
+	switch (regulator) {
+	case MTK_REGULATOR_VCORE:
+		return MT6359P_GPU11;
+	default:
+		break;
+	}
+
+	return -1;
+}
+
+void mainboard_set_regulator_vol(enum mtk_regulator regulator,
+				 uint32_t voltage_uv)
+{
+	/*
+	 * Handle the regulator that does not have a regulator ID
+	 * in its underlying implementation.
+	 */
+	if (regulator == MTK_REGULATOR_VDD1) {
+		mt6359p_set_vm18_voltage(voltage_uv);
+		return;
+	}
+
+	int id;
+
+	id = get_mt6360_regulator_id(regulator);
+	if (id >= 0) {
+		uint32_t voltage_mv = voltage_uv / 1000;
+		google_chromeec_regulator_set_voltage(id, voltage_mv, voltage_mv);
+		return;
+	}
+
+	id = get_mt6359p_regulator_id(regulator);
+	if (id >= 0) {
+		mt6359p_buck_set_voltage(id, voltage_uv);
+		return;
+	}
+
+	printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
+}
+
+uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator)
+{
+	/*
+	 * Handle the regulator that does not have a regulator ID
+	 * in its underlying implementation.
+	 */
+	if (regulator == MTK_REGULATOR_VDD1)
+		return mt6359p_get_vm18_voltage();
+
+	int id;
+
+	id = get_mt6360_regulator_id(regulator);
+	if (id >= 0) {
+		uint32_t voltage_mv = 0;
+		google_chromeec_regulator_get_voltage(id, &voltage_mv);
+		return voltage_mv * 1000;
+	}
+
+	id = get_mt6359p_regulator_id(regulator);
+	if (id >= 0)
+		return mt6359p_buck_get_voltage(id);
+
+	printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
+
+	return 0;
+}
+
+int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable)
+{
+	/* Return 0 if the regulator is already enabled or disabled. */
+	if (mainboard_regulator_is_enabled(regulator) == enable)
+		return 0;
+
+	int id;
+
+	id = get_mt6360_regulator_id(regulator);
+	if (id < 0) {
+		printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
+		return -1;
+	}
+
+	return google_chromeec_regulator_enable(id, enable);
+}
+
+uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator)
+{
+	int id;
+
+	id = get_mt6360_regulator_id(regulator);
+	if (id < 0) {
+		printk(BIOS_WARNING, "Invalid regulator ID: %d\n; assuming disabled",
+		       regulator);
+		return 0;
+	}
+
+	uint8_t enabled;
+	if (google_chromeec_regulator_is_enabled(id, &enabled) < 0) {
+		printk(BIOS_WARNING,
+		       "Failed to query regulator ID: %d\n; assuming disabled",
+		       regulator);
+		return 0;
+	}
+
+	return enabled;
+}

src/mainboard/google/asurada/romstage.c

@@ -6,6 +6,7 @@
 #include <soc/dramc_param.h>
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/mt6359p.h>
 
 /* This must be defined in chromeos.fmd in same name and size. */
 #define CALIBRATION_REGION		"RW_DDR_TRAINING"
@@ -43,6 +44,7 @@ static struct dramc_param_ops dparam_ops = {
 
 void platform_romstage_main(void)
 {
+	mt6359p_romstage_init();
 	mt_mem_init(&dparam_ops);
 	mtk_mmu_after_dram();
 }

src/mainboard/google/dedede/Kconfig

@@ -95,6 +95,7 @@ config MAINBOARD_PART_NUMBER
 	default "Wheelie" if BOARD_GOOGLE_WHEELIE
 	default "Magolor" if BOARD_GOOGLE_MAGOLOR
 	default "Metaknight" if BOARD_GOOGLE_METAKNIGHT
+	default "Lantis" if BOARD_GOOGLE_LANTIS
 
 config MAX_CPUS
 	int
@@ -125,5 +126,6 @@ config VARIANT_DIR
 	default "wheelie" if BOARD_GOOGLE_WHEELIE
 	default "magolor" if BOARD_GOOGLE_MAGOLOR
 	default "metaknight" if BOARD_GOOGLE_METAKNIGHT
+	default "lantis" if BOARD_GOOGLE_LANTIS
 
 endif #BOARD_GOOGLE_BASEBOARD_DEDEDE

src/mainboard/google/dedede/Kconfig.name

@@ -72,3 +72,9 @@ config BOARD_GOOGLE_METAKNIGHT
 	bool "-> Metaknight"
 	select BOARD_GOOGLE_BASEBOARD_DEDEDE
 	select BASEBOARD_DEDEDE_LAPTOP
+
+config BOARD_GOOGLE_LANTIS
+	bool "-> Lantis"
+	select BOARD_GOOGLE_BASEBOARD_DEDEDE
+	select BASEBOARD_DEDEDE_LAPTOP
+	select DRIVERS_GENERIC_MAX98357A

src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd

@@ -7,13 +7,15 @@ FLASH@0xff000000 0x1000000 {
 		RW_LEGACY(CBFS)@0x0 0x100000
 		RW_SECTION_A@0x100000 0x3a4800 {
 			VBLOCK_A@0x0 0x2000
-			FW_MAIN_A(CBFS)@0x2000 0x3a27c0
+			FW_MAIN_A(CBFS)@0x2000 0x2127c0
-			RW_FWID_A@0x3a47c0 0x40
+			RW_FWID_A@0x2147c0 0x40
+			ME_RW_A(CBFS)@0x214800 0x190000
 		}
 		RW_SECTION_B@0x4a4800 0x3a4800 {
 			VBLOCK_B@0x0 0x2000
-			FW_MAIN_B(CBFS)@0x2000 0x3a27c0
+			FW_MAIN_B(CBFS)@0x2000 0x2127c0
-			RW_FWID_B@0x3a47c0 0x40
+			RW_FWID_B@0x2147c0 0x40
+			ME_RW_B(CBFS)@0x214800 0x190000
 		}
 		RW_MISC@0x849000 0x36000 {
 			UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {

src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd

@@ -10,13 +10,15 @@ FLASH@0xfe000000 0x2000000 {
 		RW_LEGACY(CBFS)@0x0 0xf00000
 		RW_SECTION_A@0xf00000 0x3e0000 {
 			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x3cffc0
+			FW_MAIN_A(CBFS)@0x10000 0x23ffc0
-			RW_FWID_A@0x3dffc0 0x40
+			RW_FWID_A@0x24ffc0 0x40
+			ME_RW_A(CBFS)@0x250000 0x190000
 		}
 		RW_SECTION_B@0x12e0000 0x3e0000 {
 			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x3cffc0
+			FW_MAIN_B(CBFS)@0x10000 0x23ffc0
-			RW_FWID_B@0x3dffc0 0x40
+			RW_FWID_B@0x24ffc0 0x40
+			ME_RW_B(CBFS)@0x250000 0x190000
 		}
 		RW_MISC@0x16c0000 0x40000 {
 			UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {

src/mainboard/google/dedede/variants/lantis/include/variant/ec.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+/* Enable Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif

src/mainboard/google/dedede/variants/lantis/include/variant/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */

src/mainboard/google/dedede/variants/lantis/memory/Makefile.inc

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR

src/mainboard/google/dedede/variants/lantis/memory/dram_id.generated.txt

@@ -0,0 +1,4 @@
+DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:E       0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+K4U6E3S4AA-MGCR                0 (0000)

src/mainboard/google/dedede/variants/lantis/memory/mem_parts_used.txt

@@ -0,0 +1,3 @@
+MT53E512M32D2NP-046 WT:E
+H9HCNNNBKMMLXR-NEE
+K4U6E3S4AA-MGCR

src/mainboard/google/dedede/variants/lantis/overridetree.cb

@@ -0,0 +1,150 @@
+chip soc/intel/jasperlake
+
+	# USB Port Configuration
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Camera
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| I2C0              | Trackpad                  |
+	#| I2C1              |                           |
+	#| I2C2              | Touchscreen               |
+	#| I2C3              |                           |
+	#| I2C4              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	device domain 0 on
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Discrete Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
+						device usb 2.4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Integrated Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
+						device usb 2.7 on end
+					end
+				end
+			end
+		end # USB xHCI
+		device pci 15.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)"
+				register "wake" = "GPE0_DW0_03"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end #I2C 0
+		device pci 15.1 off  end #I2C 1
+		device pci 15.2 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0001""
+				register "desc" = ""ELAN Touchscreen""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)"
+				register "probed" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
+				register "reset_delay_ms" = "20"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "enable_delay_ms" = "1"
+				register "has_power_resource" = "1"
+				device i2c 10 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7503""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
+				register "generic.reset_delay_ms" = "50"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x5d on end
+			end
+		end # I2C 2
+		device pci 15.3 off  end #I2C 3
+		device pci 1c.7 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_DW2_03"
+				device pci 00.0 on  end
+			end
+		end # PCI Express Root Port 8 - WLAN
+		device pci 19.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Realtek RT5682""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+		end #I2C 4
+		device pci 1f.3 on
+			chip drivers/generic/max98357a
+				register "hid" = ""MX98360A""
+				register "sdmode_gpio" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
+				device generic 0 on end
+			end
+		end # Intel HDA
+	end
+end

src/mainboard/google/dedede/variants/metaknight/overridetree.cb

@@ -64,6 +64,41 @@ chip soc/intel/jasperlake
 			end
 		end # USB xHCI
 		device pci 15.0 on end
+		device pci 15.2 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 0x5d on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN6915""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end # I2C 2
 		device pci 15.3 off  end # I2C 3
 	end
 end

src/mainboard/google/hatch/romstage_spd_smbus.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 #include <spd_bin.h>

src/mainboard/google/hatch/variants/ambassador/overridetree.cb

@@ -1,4 +1,11 @@
 chip soc/intel/cannonlake
+	register "tcc_offset" = "5"	# TCC of 95C
+
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 51,
+	}"
+
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
 
@@ -205,29 +212,30 @@ chip soc/intel/cannonlake
 			chip drivers/intel/dptf
 				## Active Policy
 				register "policies.active[0]" = "{.target=DPTF_CPU,
-					.thresholds={TEMP_PCT(90, 85),
+					.thresholds={TEMP_PCT(94, 0),}}"
-						     TEMP_PCT(85, 75),
+				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_1,
-						     TEMP_PCT(80, 65),
+					.thresholds={TEMP_PCT(70, 100),
-						     TEMP_PCT(75, 55),
+						     TEMP_PCT(66, 90),
-						     TEMP_PCT(70, 45),}}"
+						     TEMP_PCT(62, 80),
-				register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
+						     TEMP_PCT(58, 70),
-					.thresholds={TEMP_PCT(50, 85),
+						     TEMP_PCT(53, 60),
-						     TEMP_PCT(47, 75),
+						     TEMP_PCT(48, 50),
-						     TEMP_PCT(45, 65),
+						     TEMP_PCT(43, 40),
-						     TEMP_PCT(42, 55),
+						     TEMP_PCT(38, 30),}}"
-						     TEMP_PCT(39, 45),}}"
 
 				## Passive Policy
-				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           93, 5000)"
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU,           95, 5000)"
-				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)"
+				register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
+				register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000)"
 
 				## Critical Policy
 				register "policies.critical[0]" = "DPTF_CRITICAL(CPU,          100, SHUTDOWN)"
-				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)"
+				register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
+				register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN)"
 
 				## Power Limits Control
 				# PL1 is fixed at 15W, avg over 28-32s interval
-				# 25-64W PL2 in 1000mW increments, avg over 28-32s interval
+				# 15-51W PL2 in 1000mW increments, avg over 28-32s interval
 				register "controls.power_limits.pl1" = "{
 					.min_power = 15000,
 					.max_power = 15000,
@@ -236,7 +244,7 @@ chip soc/intel/cannonlake
 					.granularity = 200,}"
 				register "controls.power_limits.pl2" = "{
 					.min_power = 25000,
-					.max_power = 64000,
+					.max_power = 51000,
 					.time_window_min = 28 * MSECS_PER_SEC,
 					.time_window_max = 32 * MSECS_PER_SEC,
 					.granularity = 1000,}"
@@ -394,8 +402,11 @@ chip soc/intel/cannonlake
 				register "device_index" = "0"
 				device pci 00.0 on end
 			end
+			register "PcieRpSlotImplemented[6]" = "1"
 		end # RTL8111H Ethernet NIC
-		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+		device pci 1d.2 on	# PCI Express Port 11 (X2 NVMe)
+			register "PcieRpSlotImplemented[10]" = "1"
+		end
 		device pci 1e.3 off end # GSPI #1
 	end
 

src/mainboard/google/hatch/variants/baseboard/mainboard.c

@@ -2,6 +2,7 @@
 
 #include <baseboard/variants.h>
 #include <chip.h>
+#include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci_ids.h>

src/mainboard/google/hatch/variants/dratini/gpio.c

@@ -16,6 +16,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_A19, NONE),
 	/* C12 : FPMCU_PCH_BOOT1 */
 	PAD_CFG_GPO(GPP_C12, 0, DEEP),
+	/* D4  : Camera Privacy Status */
+	PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH),
 	/* F1  : NC */
 	PAD_NC(GPP_F1, NONE),
 	/* F3  : MEM_STRAP_3 */

src/mainboard/google/hatch/variants/dratini/overridetree.cb

@@ -69,6 +69,19 @@ chip soc/intel/cannonlake
 	register "ScsEmmcHs400Enabled" = "1"
 
 	device domain 0 on
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						# The Linux Kernel does not allow an inverted BOTH_EDGE irq
+						# So we need to use GpioIO() instead of GpioInt()
+						# https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt
+						register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)"
+						device usb 2.6 on end
+					end
+				end
+			end
+                end # USB xHCI
 		device pci 15.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""ELAN0000""

src/mainboard/google/hatch/variants/jinlon/mainboard.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <device/device.h>
 #include <drivers/gfx/generic/chip.h>

src/mainboard/google/kukui/boardid.c

@@ -13,7 +13,7 @@
 #include <device/i2c_simple.h>
 #include <drivers/camera/cros_camera.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/auxadc.h>
+#include <soc/auxadc_common.h>
 #include <soc/i2c.h>
 #include <soc/pmic_wrap_common.h>
 #include <string.h>
@@ -69,7 +69,7 @@ static const int *adc_voltages[] = {
 
 static uint32_t get_adc_index(unsigned int channel)
 {
-	int value = auxadc_get_voltage(channel);
+	int value = auxadc_get_voltage_uv(channel);
 
 	assert(channel < ARRAY_SIZE(adc_voltages));
 	const int *voltages = adc_voltages[channel];

src/mainboard/google/kukui/mainboard.c

@@ -91,7 +91,7 @@ static void power_on_panel(struct panel_description *panel)
 	gpio_output(GPIO_PPVARN_LCD_EN, 1);
 	gpio_output(GPIO_PP1800_LCM_EN, 1);
 	gpio_output(GPIO_PP3300_LCM_EN, 1);
-	mdelay(6);
+	mdelay(15);
 	gpio_output(GPIO_LCM_RST_1V8, 1);
 	mdelay(6);
 }

src/mainboard/google/octopus/variants/bobba/overridetree.cb

@@ -210,6 +210,20 @@ chip soc/intel/apollolake
 				register "has_power_resource" = "1"
 				device i2c 39 on end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GTCH7502""
+				register "generic.desc" = ""G2TOUCH Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+				register "generic.reset_delay_ms" = "70"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 40 on end
+			end
 		end	# - I2C 7
 	end
 

src/mainboard/google/poppy/variants/nami/memory.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <console/console.h>
 #include <gpio.h>
 #include <variant/gpio.h>
 #include <string.h>

src/mainboard/google/reef/variants/baseboard/memory.c

@@ -138,6 +138,13 @@ static const struct lpddr4_sku skus[] = {
 		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.part_num = "K4F8E3S4HD-MGCL",
 	},
+	/* NT6AN256T32AV-J2 - both logical channels */
+	[9] = {
+		.speed = LP4_SPEED_2400,
+		.ch0_rank_density = LP4_8Gb_DENSITY,
+		.ch1_rank_density = LP4_8Gb_DENSITY,
+		.part_num = "NT6AN256T32AV-J2",
+	},
 };
 
 static const struct lpddr4_cfg lp4cfg = {