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arch/x86: Add postcar_frame_common_mtrrs()

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As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.

Add possibility for the platform to skip these if
required.

Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-09 11:41:15 +03:00
parent 5bc641afeb
commit 544878b563
15 changed files with 24 additions and 74 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/e7505/memmap.c
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@@ -54,6 +54,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
* operations when source is left as UC.
*/
pcf->skip_common_mtrr = 1;
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);

7
src/northbridge/intel/gm45/memmap.c
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@@ -138,13 +138,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/

6
src/northbridge/intel/haswell/memmap.c
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@@ -57,12 +57,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.

7
src/northbridge/intel/i440bx/memmap.c
View File

@@ -72,13 +72,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache CBMEM region as WB. */
top_of_ram = (uintptr_t)cbmem_top();
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,

7
src/northbridge/intel/i945/memmap.c
View File

@@ -104,13 +104,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/

7
src/northbridge/intel/nehalem/memmap.c
View File

@@ -62,13 +62,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
* above top of the ram. This satisfies MTRR alignment requirement
* with different TSEG size configurations.

7
src/northbridge/intel/pineview/memmap.c
View File

@@ -154,13 +154,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/

7
src/northbridge/intel/sandybridge/memmap.c
View File

@@ -61,13 +61,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
top_of_ram = (uintptr_t)cbmem_top();
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
* ram under 4GiB is the start of the TSEG region. It is required to

7
src/northbridge/intel/x4x/memmap.c
View File

@@ -149,13 +149,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
* ram to cover both cbmem as the TSEG region.
*/