soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI

Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/amd/cezanne/Kconfig

@@ -13,6 +13,7 @@ config SOC_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select FSP_COMPRESS_FSP_M_LZMA
 	select FSP_COMPRESS_FSP_S_LZMA
 	select HAVE_CF9_RESET
@@ -30,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
 	select SOC_AMD_COMMON_BLOCK_SMBUS
 	select SOC_AMD_COMMON_BLOCK_SMI
+	select SOC_AMD_COMMON_BLOCK_SPI
 	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SSE2