soc/intel/cannonlake: Add FSP UPD for minimum assertion width

Expose the FSP tunables for the chipset minimum assertion width
settings which can be configured per-board.

The defaults appear to be different from what is listed in the FSP
header documentation so I tried to list what the actual default is
based on the source rather than what is stated the header comments.

Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>

src/soc/intel/cannonlake/chip.h

@@ -222,6 +222,43 @@ struct soc_intel_cannonlake_config {
 	 */
 	uint32_t PrmrrSize;
 	uint8_t PmTimerDisabled;
+
+	/*
+	 * SLP_S3 Minimum Assertion Width Policy
+	 *  1 = 60us
+	 *  2 = 1ms (default)
+	 *  3 = 50ms
+	 *  4 = 2s
+	 */
+	uint8_t PchPmSlpS3MinAssert;
+
+	/*
+	 * SLP_S4 Minimum Assertion Width Policy
+	 *  1 = 1s
+	 *  2 = 2s
+	 *  3 = 3s
+	 *  4 = 4s (default)
+	 */
+	uint8_t PchPmSlpS4MinAssert;
+
+	/*
+	 * SLP_SUS Minimum Assertion Width Policy
+	 *  1 = 0ms
+	 *  2 = 500ms
+	 *  3 = 1s (default)
+	 *  4 = 4s
+	 */
+	uint8_t PchPmSlpSusMinAssert;
+
+	/*
+	 * SLP_A Minimum Assertion Width Policy
+	 *  1 = 0ms
+	 *  2 = 4s
+	 *  3 = 98ms (default)
+	 *  4 = 2s
+	 */
+	uint8_t PchPmSlpAMinAssert;
+
 	/* Desired platform debug type. */
 	enum {
 		DebugConsent_Disabled,