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soc/nvidia: Drop unneeded empty lines

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Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2020-08-19 21:44:36 +02:00
committed by Michael Niewöhner
parent cb795f0ff9
commit 555c3b1d9b
18 changed files with 0 additions and 76 deletions
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1
src/soc/nvidia/tegra/dc.h
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@@ -348,7 +348,6 @@ struct display_controller {
}; };
check_member(display_controller, winbuf, 0x800 * 4); check_member(display_controller, winbuf, 0x800 * 4);
/* DC_CMD_DISPLAY_COMMAND 0x032 */ /* DC_CMD_DISPLAY_COMMAND 0x032 */
#define DISP_COMMAND_RAISE (1 << 0) #define DISP_COMMAND_RAISE (1 << 0)
#define DISP_CTRL_MODE_STOP (0 << 5) #define DISP_CTRL_MODE_STOP (0 << 5)

1
src/soc/nvidia/tegra/displayport.h
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@@ -326,7 +326,6 @@ struct tegra_dc_dp_data {
int enabled; int enabled;
}; };
/* DPCD definitions */ /* DPCD definitions */
/* you know, all the vendors pick their own set of defines. /* you know, all the vendors pick their own set of defines.
* All of them. * All of them.

1
src/soc/nvidia/tegra/usb.h
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@@ -3,7 +3,6 @@
#ifndef __SOC_NVIDIA_TEGRA_USB_H__ #ifndef __SOC_NVIDIA_TEGRA_USB_H__
#define __SOC_NVIDIA_TEGRA_USB_H__ #define __SOC_NVIDIA_TEGRA_USB_H__
enum usb_phy_type { /* For use in lpm_ctrl[31:29] */ enum usb_phy_type { /* For use in lpm_ctrl[31:29] */
USB_PHY_UTMIP = 0, USB_PHY_UTMIP = 0,
USB_PHY_ULPI = 2, USB_PHY_ULPI = 2,

1
src/soc/nvidia/tegra124/dp.c
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@@ -616,7 +616,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
if (link_cfg->hblank_sym < 0) if (link_cfg->hblank_sym < 0)
link_cfg->hblank_sym = 0; link_cfg->hblank_sym = 0;
/* Refer to dev_disp.ref for more information. */ /* Refer to dev_disp.ref for more information. */
/* # symbols/vblank = ((SetRasterBlankStart.X - */ /* # symbols/vblank = ((SetRasterBlankStart.X - */
/* SetRasterBlankEen.X - 25) * link_clk / pclk) */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */

42
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
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@@ -12,21 +12,15 @@ enum {
SYSCTR_CTLR_BASE = 0x700f0000 SYSCTR_CTLR_BASE = 0x700f0000
}; };
/* UP tag registers. */ /* UP tag registers. */
static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0);
enum { enum {
UP_TAG_AVP = 0xaaaaaaaa UP_TAG_AVP = 0xaaaaaaaa
}; };
/* Timer registers. */ /* Timer registers. */
static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10);
/* Clock and reset controller registers. */ /* Clock and reset controller registers. */
static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4);
enum { enum {
@@ -152,14 +146,9 @@ enum {
CLR_NONCPURESET = 0x1 << 29 CLR_NONCPURESET = 0x1 << 29
}; };
/* Reset vector. */ /* Reset vector. */
static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100);
/* Flow controller registers. */ /* Flow controller registers. */
static uint32_t *flow_ctlr_halt_cop_events_ptr = static uint32_t *flow_ctlr_halt_cop_events_ptr =
(void *)(FLOW_CTLR_BASE + 0x4); (void *)(FLOW_CTLR_BASE + 0x4);
@@ -185,7 +174,6 @@ enum {
RAM_REPAIR_STS = 0x1 << 1, RAM_REPAIR_STS = 0x1 << 1,
}; };
/* Power management controller registers. */ /* Power management controller registers. */
enum { enum {
PARTID_CRAIL = 0, PARTID_CRAIL = 0,
@@ -220,8 +208,6 @@ enum {
PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT
}; };
/* Memory controller registers. */ /* Memory controller registers. */
static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
@@ -232,8 +218,6 @@ enum {
VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1
}; };
/* System counter registers. */ /* System counter registers. */
static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0);
enum { enum {
@@ -243,10 +227,7 @@ enum {
static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20);
/* Utility functions. */ /* Utility functions. */
static __always_inline void __noreturn halt(void) static __always_inline void __noreturn halt(void)
{ {
for (;;); for (;;);
@@ -285,10 +266,7 @@ static void udelay(unsigned int usecs)
; ;
} }
/* Accessors. */ /* Accessors. */
static int wakeup_on_lp(void) static int wakeup_on_lp(void)
{ {
return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP);
@@ -304,10 +282,7 @@ static unsigned int get_osc_freq(void)
return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
} }
/* Clock configuration. */ /* Clock configuration. */
static void config_oscillator(void) static void config_oscillator(void)
{ {
// Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy
@@ -416,10 +391,7 @@ static void enable_cpu_clocks(void)
write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP);
} }
/* Function unit configuration. */ /* Function unit configuration. */
static void config_core_sight(void) static void config_core_sight(void)
{ {
// Enable the CoreSight clock. // Enable the CoreSight clock.
@@ -449,10 +421,7 @@ static void config_mselect(void)
write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST);
} }
/* Resets. */ /* Resets. */
static void clear_cpu_resets(void) static void clear_cpu_resets(void)
{ {
// Take the non-cpu of the G and LP clusters out of reset. // Take the non-cpu of the G and LP clusters out of reset.
@@ -471,10 +440,7 @@ static void clear_cpu_resets(void)
CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3);
} }
/* RAM repair */ /* RAM repair */
void ram_repair(void) void ram_repair(void)
{ {
// Request Cluster0 RAM repair. // Request Cluster0 RAM repair.
@@ -490,9 +456,7 @@ void ram_repair(void)
; ;
} }
/* Power. */ /* Power. */
static void power_on_partition(unsigned int id) static void power_on_partition(unsigned int id)
{ {
uint32_t bit = 0x1 << id; uint32_t bit = 0x1 << id;
@@ -544,10 +508,7 @@ static void power_on_main_cpu(void)
write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer);
} }
/* Entry point. */ /* Entry point. */
void lp0_resume(void) void lp0_resume(void)
{ {
// If not on the AVP, reset. // If not on the AVP, reset.
@@ -608,10 +569,7 @@ void lp0_resume(void)
FLOW_MODE_STOP | EVENT_JTAG); FLOW_MODE_STOP | EVENT_JTAG);
} }
/* Header. */ /* Header. */
extern uint8_t blob_data; extern uint8_t blob_data;
extern uint8_t blob_data_size; extern uint8_t blob_data_size;
extern uint8_t blob_total_size; extern uint8_t blob_total_size;

1
src/soc/nvidia/tegra124/sdram.c
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@@ -11,7 +11,6 @@
#include <soc/sdram.h> #include <soc/sdram.h>
#include <symbols.h> #include <symbols.h>
static void sdram_patch(uintptr_t addr, uint32_t value) static void sdram_patch(uintptr_t addr, uint32_t value)
{ {
if (addr) if (addr)

3
src/soc/nvidia/tegra124/spi.c
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@@ -335,7 +335,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi)
spi_delay(spi, dma_blk - count); spi_delay(spi, dma_blk - count);
} }
static int fifo_error(struct tegra_spi_channel *spi) static int fifo_error(struct tegra_spi_channel *spi)
{ {
return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0;
@@ -523,8 +522,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
if (spi->dma_in) if (spi->dma_in)
dma_start(spi->dma_in); dma_start(spi->dma_in);
} }
static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) static int tegra_spi_dma_finish(struct tegra_spi_channel *spi)

1
src/soc/nvidia/tegra124/uart.c
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@@ -5,7 +5,6 @@
#include <console/uart.h> #include <console/uart.h>
#include <drivers/uart/uart8250reg.h> #include <drivers/uart/uart8250reg.h>
struct tegra124_uart { struct tegra124_uart {
union { union {
uint32_t thr; // Transmit holding register. uint32_t thr; // Transmit holding register.

1
src/soc/nvidia/tegra210/bootblock.c
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@@ -179,7 +179,6 @@ void tegra210_main(void)
pmc_print_rst_status(); pmc_print_rst_status();
bootblock_mainboard_init(); bootblock_mainboard_init();
printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n"); printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n");

1
src/soc/nvidia/tegra210/dc.c
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@@ -91,7 +91,6 @@ int update_display_mode(struct display_controller *disp_ctrl,
WRITEL(config->vsync_width << 16 | config->hsync_width, WRITEL(config->vsync_width << 16 | config->hsync_width,
&disp_ctrl->disp.sync_width); &disp_ctrl->disp.sync_width);
WRITEL((config->vback_porch << 16) | config->hback_porch, WRITEL((config->vback_porch << 16) | config->hback_porch,
&disp_ctrl->disp.back_porch); &disp_ctrl->disp.back_porch);

2
src/soc/nvidia/tegra210/dp.c
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@@ -631,7 +631,6 @@ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
if (link_cfg->hblank_sym < 0) if (link_cfg->hblank_sym < 0)
link_cfg->hblank_sym = 0; link_cfg->hblank_sym = 0;
/* Refer to dev_disp.ref for more information. */ /* Refer to dev_disp.ref for more information. */
/* # symbols/vblank = ((SetRasterBlankStart.X - */ /* # symbols/vblank = ((SetRasterBlankStart.X - */
/* SetRasterBlankEen.X - 25) * link_clk / pclk) */ /* SetRasterBlankEen.X - 25) * link_clk / pclk) */
@@ -1189,7 +1188,6 @@ static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
int j; int j;
u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4); u32 mask = 0xffff >> ((4 - link_cfg->lane_count) * 4);
printk(BIOS_INFO, "dp: %s\n", __func__); printk(BIOS_INFO, "dp: %s\n", __func__);
tegra_dc_sor_set_lane_parm(sor, link_cfg); tegra_dc_sor_set_lane_parm(sor, link_cfg);

3
src/soc/nvidia/tegra210/dsi.c
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@@ -434,7 +434,6 @@ static int tegra_output_dsi_enable(struct tegra_dsi *dsi,
return 0; return 0;
} }
static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
unsigned int vrefresh) unsigned int vrefresh)
{ {
@@ -520,8 +519,6 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi,
return plld/1000000; return plld/1000000;
} }
static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
{ {
unsigned long value; unsigned long value;

1
src/soc/nvidia/tegra210/include/soc/ccplex.h
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@@ -3,7 +3,6 @@
#ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__ #ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__
#define __SOC_NVIDIA_TEGRA210_CCPLEX_H__ #define __SOC_NVIDIA_TEGRA210_CCPLEX_H__
#define MTS_LOAD_ADDRESS 0x82000000 #define MTS_LOAD_ADDRESS 0x82000000
/* Prepare the clocks and rails to start the cpu. */ /* Prepare the clocks and rails to start the cpu. */

1
src/soc/nvidia/tegra210/include/soc/id.h
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@@ -3,7 +3,6 @@
#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ #ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__
#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ #define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__
#include <device/mmio.h> #include <device/mmio.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>

1
src/soc/nvidia/tegra210/include/soc/mipi-phy.h
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@@ -2,7 +2,6 @@
#ifndef _TEGRA_MIPI_PHY_H #ifndef _TEGRA_MIPI_PHY_H
#define _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H
/* /*
* Macros for calculating the phy timings * Macros for calculating the phy timings
*/ */

11
src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
View File

@@ -26,7 +26,6 @@ enum {
UP_TAG_AVP = 0xaaaaaaaa UP_TAG_AVP = 0xaaaaaaaa
}; };
/* APB Misc JTAG Configuration Register */ /* APB Misc JTAG Configuration Register */
static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24); static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24);
enum { enum {
@@ -40,7 +39,6 @@ enum {
CFG2TMC_RAM_SVOP_PDP_VAL_2 = 0x2 << 24, CFG2TMC_RAM_SVOP_PDP_VAL_2 = 0x2 << 24,
}; };
/* PINMUX registers. */ /* PINMUX registers. */
static uint32_t *pinmux_pwr_i2c_scl_ptr = (void *)(PINMUX_BASE + 0xdc); static uint32_t *pinmux_pwr_i2c_scl_ptr = (void *)(PINMUX_BASE + 0xdc);
static uint32_t *pinmux_pwr_i2c_sda_ptr = (void *)(PINMUX_BASE + 0xe0); static uint32_t *pinmux_pwr_i2c_sda_ptr = (void *)(PINMUX_BASE + 0xe0);
@@ -57,7 +55,6 @@ enum {
static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10);
static uint32_t *timer_us_cfg_ptr = (void *)(TIMER_BASE + 0x14); static uint32_t *timer_us_cfg_ptr = (void *)(TIMER_BASE + 0x14);
/* Clock and reset controller registers. */ /* Clock and reset controller registers. */
static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4);
enum { enum {
@@ -264,7 +261,6 @@ enum {
ACTIVE_SLOW = 0x1 << 0 ACTIVE_SLOW = 0x1 << 0
}; };
/* Power management controller registers. */ /* Power management controller registers. */
enum { enum {
PARTID_CRAIL = 0, PARTID_CRAIL = 0,
@@ -346,7 +342,6 @@ enum {
static uint32_t *sb_aa64_reset_low = (void *)(SECURE_BOOT_BASE + 0x30); static uint32_t *sb_aa64_reset_low = (void *)(SECURE_BOOT_BASE + 0x30);
static uint32_t *sb_aa64_reset_high = (void *)(SECURE_BOOT_BASE + 0x34); static uint32_t *sb_aa64_reset_high = (void *)(SECURE_BOOT_BASE + 0x34);
/* EMC registers */ /* EMC registers */
static uint32_t *pmacro_cfg_pm_global = (void *)(EMC_BASE + 0xc30); static uint32_t *pmacro_cfg_pm_global = (void *)(EMC_BASE + 0xc30);
enum { enum {
@@ -408,7 +403,6 @@ enum {
#define MAX77621_VOUT_VAL (0x80 | 0x27) #define MAX77621_VOUT_VAL (0x80 | 0x27)
#define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8)) #define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8))
/* Utility functions. */ /* Utility functions. */
static __always_inline void __noreturn halt(void) static __always_inline void __noreturn halt(void)
@@ -592,7 +586,6 @@ static void enable_select_cpu_clocks(void)
udelay(10); udelay(10);
} }
/* Function unit configuration. */ /* Function unit configuration. */
static void config_core_sight(void) static void config_core_sight(void)
@@ -609,7 +602,6 @@ static void config_core_sight(void)
write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST);
} }
/* RAM repair */ /* RAM repair */
void ram_repair(void) void ram_repair(void)
@@ -621,7 +613,6 @@ void ram_repair(void)
; ;
} }
/* Power. */ /* Power. */
static void power_on_partition(unsigned int id) static void power_on_partition(unsigned int id)
@@ -764,7 +755,6 @@ static void mbist_workaround(void)
write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */
write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00);
clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr);
clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0; clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0;
write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared); write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared);
@@ -1085,7 +1075,6 @@ void lp0_resume(void)
FLOW_MODE_STOP | EVENT_JTAG); FLOW_MODE_STOP | EVENT_JTAG);
} }
/* Header. */ /* Header. */
extern uint8_t blob_data; extern uint8_t blob_data;

3
src/soc/nvidia/tegra210/spi.c
View File

@@ -319,7 +319,6 @@ static void tegra_spi_wait(struct tegra_spi_channel *spi)
ASSERT(spi_byte_count(spi) == dma_blk_count); ASSERT(spi_byte_count(spi) == dma_blk_count);
} }
static int fifo_error(struct tegra_spi_channel *spi) static int fifo_error(struct tegra_spi_channel *spi)
{ {
return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0;
@@ -550,8 +549,6 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi)
setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
if (spi->dma_in) if (spi->dma_in)
dma_start(spi->dma_in); dma_start(spi->dma_in);
} }
static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) static int tegra_spi_dma_finish(struct tegra_spi_channel *spi)

1
src/soc/nvidia/tegra210/uart.c
View File

@@ -26,7 +26,6 @@ struct tegra210_uart {
uint32_t msr; // Modem status register. uint32_t msr; // Modem status register.
} __packed; } __packed;
static struct tegra210_uart * const uart_ptr = static struct tegra210_uart * const uart_ptr =
(void *)CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; (void *)CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;