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mb/google/brox: support ISH

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Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main
firmware name so ISH shim loader can load firmware from file system.

ISH also need to be enabled if STORAGE_UFS is set.

BUG=b:280329972
TEST= Set bit CBI FW_CONFIG bit 21
      Boot Brox board, check that ISH is enabled and loaded
      lspci shows: 00:12.0 Serial controller: Intel Corporation Alder
Lake-P Integrated Sensor Hub (rev 01).

Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
This commit is contained in:
Li Feng
2024-02-27 21:47:15 -08:00
committed by Felix Held
parent 929ef5f7f1
commit 55a7d90a50
3 changed files with 39 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/brox/variants/baseboard/brox/gpio.c
View File

@@ -68,7 +68,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_A15 : [NF1: USB_OC2# NF2: DDSP_HPD4 NF4: DISP_MISC4 NF6: USB_C_GPP_A15] ==> USB_A1_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* GPP_A16 : [NF1: USB_OC3# NF4: ISH_GP5 NF6: USB_C_GPP_A16] ==> TABLET_MODE_ODL */
PAD_CFG_GPI(GPP_A16, NONE, PLTRST),
PAD_NC(GPP_A16, NONE),
/* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> SOC_GPP_A17 */
PAD_NC(GPP_A17, NONE),
/* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> HDMI_HPD */
@@ -95,9 +95,9 @@ static const struct pad_config gpio_table[] = {
/* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */
PAD_NC(GPP_B4, NONE),
/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */
PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
PAD_NC(GPP_B5, NONE),
/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> ISH_I2C_SENSOR_SCL */
PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
PAD_NC(GPP_B6, NONE),
/* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> SOC_I2C3_SDA (NC) */
PAD_NC(GPP_B7, NONE),
/* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */
@@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 NF6: USB_C_GPP_B14] ==> ACZ_SPKR (NC) */
PAD_NC(GPP_B14, NONE),
/* GPP_B15 : [NF2: TIME_SYNC0 NF5: ISH_GP7 NF6: USB_C_GPP_B15] ==> LID_OPEN_Q */
PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
PAD_NC(GPP_B15, NONE),
/* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */
/* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */
PAD_NC(GPP_B16, NONE),
@@ -166,9 +166,9 @@ static const struct pad_config gpio_table[] = {
/* GPP_D12 : [NF1: ISH_SPI_MOSI NF2: DDP4_CTRLDATA NF4: TBT_LSX3_RXD NF5: BSSB_LS3_TX NF6: USB_C_GPP_D12 NF7: GSPI2_MOSI] ==> SOC_GPP_D12 (NC) */
PAD_NC(GPP_D12, NONE),
/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
PAD_NC(GPP_D13, NONE),
/* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */
PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
PAD_NC(GPP_D14, NONE),
/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */
PAD_NC(GPP_D15, NONE),
/* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */

27
src/mainboard/google/brox/variants/brox/fw_config.c
View File

@@ -1,8 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
#include <fw_config.h>
#include <gpio.h>
#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a))
static const struct pad_config ish_enable_pads[] = {
/* GPP_B5 : ISH I2C0_SDA */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
/* GPP_B6 : ISH_I2C0_SCL */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
/* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* GPP_D2 : ISH_GP2, SOC_ISH_ACCEL_INT_L */
PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
/* GPP_D3 : ISH_GP3, SOC_ISH_IMU_INT_L */
PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
/* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5),
/* GPP_A16 : ISH_GP5, TABLET_MODE_ODL */
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
};
static void fw_config_handle(void *unused)
{
if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
printk(BIOS_INFO, "Configure GPIOs for ISH.\n");
gpio_configure_pads(ish_enable_pads, ARRAY_SIZE(ish_enable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

6
src/mainboard/google/brox/variants/brox/overridetree.cb
View File

@@ -21,6 +21,10 @@ fw_config
option UFC_NONE 0
option UFC_OV2740 1
end
field ISH 21
option ISH_DISABLE 0
option ISH_ENABLE 1
end
end
chip soc/intel/alderlake
@@ -296,9 +300,11 @@ chip soc/intel/alderlake
end
device ref ish on
chip drivers/intel/ish
register "firmware_name" = ""brox_ish.bin""
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
probe ISH ISH_ENABLE
probe STORAGE STORAGE_UFS
end
device ref ufs on