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Autogenerate MacBookAir4,2

Browse Source 
Just ran autoport on the data from MacBookAir4,2

Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11840
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Vladimir Serbinenko
2015-05-29 22:07:29 +02:00
parent 52262662da
commit 55f3e2fd00
16 changed files with 867 additions and 0 deletions
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68
src/mainboard/apple/macbookair4_2/Kconfig Normal file
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if BOARD_APPLE_MACBOOKAIR4_2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ROMSIZE_KB_8192
select CPU_INTEL_SOCKET_RPGA989
select EC_ACPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_EDID
select INTEL_INT15
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SANDYBRIDGE_LVDS
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select SYSTEM_TYPE_LAPTOP
select VGA
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default apple/macbookair4_2
config MAINBOARD_PART_NUMBER
string
default "MacBookAir4,2"
config VGA_BIOS_FILE
string
default "pci8086,0116.rom"
config VGA_BIOS_ID
string
default "8086,0116"
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x7270
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x8086
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config DRAM_RESET_GATE_GPIO # FIXME: check this
int
default 60
config MAX_CPUS
int
default 8
config USBDEBUG_HCD_INDEX # FIXME: check this
int
default 2
endif

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src/mainboard/apple/macbookair4_2/Kconfig.name Normal file
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config BOARD_APPLE_MACBOOKAIR4_2
bool "MacBookAir4,2"

3
src/mainboard/apple/macbookair4_2/Makefile.inc Normal file
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romstage-y += early_southbridge.c
romstage-y += gpio.c
ramstage-y += gnvs.c

7
src/mainboard/apple/macbookair4_2/acpi/ec.asl Normal file
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Device(EC)
{
Name (_HID, EISAID("PNP0C09"))
Name (_UID, 0)
Name (_GPE, 23)
/* FIXME: EC support */
}

10
src/mainboard/apple/macbookair4_2/acpi/platform.asl Normal file
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Method(_WAK,1)
{
/* FIXME: EC support */
Return(Package(){0,0})
}
Method(_PTS,1)
{
/* FIXME: EC support */
}

0
src/mainboard/apple/macbookair4_2/acpi/superio.asl Normal file
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1
src/mainboard/apple/macbookair4_2/acpi_tables.c Normal file
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/* dummy */

4
src/mainboard/apple/macbookair4_2/board_info.txt Normal file
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Category: laptop
ROM protocol: SPI
Flashrom support: n
FIXME: put ROM package, ROM socketed, Release year

119
src/mainboard/apple/macbookair4_2/devicetree.cb Normal file
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chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
register "gfx.link_frequency_270_mhz" = "0"
register "gfx.lvds_dual_channel" = "0"
register "gfx.lvds_num_lanes" = "1"
register "gfx.ndid" = "3"
register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_cpu_backlight" = "0x00001312"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_port_select" = "1"
register "gpu_panel_power_backlight_off_delay" = "2000"
register "gpu_panel_power_backlight_on_delay" = "10"
register "gpu_panel_power_cycle_delay" = "6"
register "gpu_panel_power_down_delay" = "500"
register "gpu_panel_power_up_delay" = "2000"
register "gpu_pch_backlight" = "0x13121312"
device cpu_cluster 0x0 on
chip cpu/intel/socket_rPGA989
device lapic 0x0 on
end
end
chip cpu/intel/model_206ax # FIXME: check all registers
register "c1_acpower" = "1"
register "c1_battery" = "1"
register "c2_acpower" = "3"
register "c2_battery" = "3"
register "c3_acpower" = "5"
register "c3_battery" = "5"
device lapic 0xacac off
end
end
end
device domain 0x0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "docking_supported" = "0"
register "gen1_dec" = "0x000c0681"
register "gen2_dec" = "0x000c1641"
register "gen3_dec" = "0x001c0301"
register "gen4_dec" = "0x00fc0701"
register "gpi7_routing" = "2"
register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x1"
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x8086 0x7270
end
device pci 16.1 off # Management Engine Interface 2
end
device pci 16.2 off # Management Engine IDE-R
end
device pci 16.3 off # Management Engine KT
end
device pci 19.0 off # Intel Gigabit Ethernet
end
device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c
subsystemid 0x8086 0x7270
end
device pci 1b.0 on # High Definition Audio Audio controller
subsystemid 0x8086 0x7270
end
device pci 1c.0 on # PCIe Port #1
subsystemid 0x8086 0x7270
end
device pci 1c.1 on # PCIe Port #2
subsystemid 0x8086 0x7270
end
device pci 1c.2 off # PCIe Port #3
end
device pci 1c.3 off # PCIe Port #4
end
device pci 1c.4 off # PCIe Port #5
end
device pci 1c.5 off # PCIe Port #6
end
device pci 1c.6 off # PCIe Port #7
end
device pci 1c.7 off # PCIe Port #8
end
device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27
subsystemid 0x8086 0x7270
end
device pci 1e.0 off # PCI bridge
end
device pci 1f.0 on # LPC bridge PCI-LPC bridge
subsystemid 0x8086 0x7270
end
device pci 1f.2 on # SATA Controller 1
subsystemid 0x8086 0x7270
end
device pci 1f.3 on # SMBus
subsystemid 0x8086 0x7270
end
device pci 1f.5 off # SATA Controller 2
end
device pci 1f.6 off # Thermal
end
end
device pci 00.0 on # Host bridge Host bridge
subsystemid 0x106b 0x00eb
end
device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101
subsystemid 0x106b 0x00eb
end
device pci 02.0 on # Internal graphics VGA controller
subsystemid 0x106b 0x00eb
end
device pci 1a.7 on
subsystemid 0x8086 0x7270
end
device pci 1d.7 on
subsystemid 0x8086 0x7270
end
end
end

29
src/mainboard/apple/macbookair4_2/dsdt.asl Normal file
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x03, // DSDT revision: ACPI v3.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20141018 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
#include <cpu/intel/model_206ax/acpi/cpu.asl>
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
}
}
}

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src/mainboard/apple/macbookair4_2/early_southbridge.c Normal file
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#include <stdint.h>
#include <string.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h>
#include "northbridge/intel/sandybridge/sandybridge.h"
#include "northbridge/intel/sandybridge/raminit_native.h"
#include "southbridge/intel/bd82x6x/pch.h"
#include "southbridge/intel/bd82x6x/gpio.h"
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
void pch_enable_lpc(void)
{
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701);
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
}
void rcba_config(void)
{
/* Disable devices. */
RCBA32(0x3414) = 0x00000020;
RCBA32(0x3418) = 0x1ffc0ee3;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
};
/* FIXME: Put proper SPD map here. */
void mainboard_get_spd(spd_raw_data *spd)
{
read_spd(&spd[0], 0x50);
read_spd(&spd[1], 0x51);
read_spd(&spd[2], 0x52);
read_spd(&spd[3], 0x53);
}

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src/mainboard/apple/macbookair4_2/gnvs.c Normal file
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#include <southbridge/intel/bd82x6x/nvs.h>
/* FIXME: check this function. */
void acpi_create_gnvs(global_nvs_t *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
// the lid is open by default.
gnvs->lids = 1;
gnvs->tcrt = 100;
gnvs->tpsv = 90;
}

433
src/mainboard/apple/macbookair4_2/gpio.c Normal file
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#include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO,
.gpio1 = GPIO_MODE_GPIO,
.gpio2 = GPIO_MODE_GPIO,
.gpio3 = GPIO_MODE_GPIO,
.gpio4 = GPIO_MODE_GPIO,
.gpio5 = GPIO_MODE_GPIO,
.gpio6 = GPIO_MODE_GPIO,
.gpio7 = GPIO_MODE_GPIO,
.gpio8 = GPIO_MODE_GPIO,
.gpio9 = GPIO_MODE_GPIO,
.gpio10 = GPIO_MODE_GPIO,
.gpio11 = GPIO_MODE_GPIO,
.gpio12 = GPIO_MODE_GPIO,
.gpio13 = GPIO_MODE_GPIO,
.gpio14 = GPIO_MODE_GPIO,
.gpio15 = GPIO_MODE_GPIO,
.gpio16 = GPIO_MODE_GPIO,
.gpio17 = GPIO_MODE_GPIO,
.gpio18 = GPIO_MODE_NATIVE,
.gpio19 = GPIO_MODE_GPIO,
.gpio20 = GPIO_MODE_GPIO,
.gpio21 = GPIO_MODE_GPIO,
.gpio22 = GPIO_MODE_GPIO,
.gpio23 = GPIO_MODE_GPIO,
.gpio24 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
.gpio26 = GPIO_MODE_NATIVE,
.gpio27 = GPIO_MODE_GPIO,
.gpio28 = GPIO_MODE_GPIO,
.gpio29 = GPIO_MODE_GPIO,
.gpio30 = GPIO_MODE_NATIVE,
.gpio31 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio16 = GPIO_DIR_OUTPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_OUTPUT,
.gpio22 = GPIO_DIR_INPUT,
.gpio23 = GPIO_DIR_OUTPUT,
.gpio24 = GPIO_DIR_INPUT,
.gpio25 = GPIO_DIR_INPUT,
.gpio26 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_INPUT,
.gpio28 = GPIO_DIR_INPUT,
.gpio29 = GPIO_DIR_INPUT,
.gpio30 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_HIGH,
.gpio3 = GPIO_LEVEL_LOW,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_LOW,
.gpio7 = GPIO_LEVEL_HIGH,
.gpio8 = GPIO_LEVEL_LOW,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_LOW,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_LOW,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio19 = GPIO_LEVEL_LOW,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio21 = GPIO_LEVEL_LOW,
.gpio22 = GPIO_LEVEL_LOW,
.gpio23 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_HIGH,
.gpio25 = GPIO_LEVEL_HIGH,
.gpio26 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_HIGH,
.gpio28 = GPIO_LEVEL_HIGH,
.gpio29 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
.gpio31 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio0 = GPIO_RESET_PWROK,
.gpio1 = GPIO_RESET_PWROK,
.gpio2 = GPIO_RESET_PWROK,
.gpio3 = GPIO_RESET_PWROK,
.gpio4 = GPIO_RESET_PWROK,
.gpio5 = GPIO_RESET_PWROK,
.gpio6 = GPIO_RESET_PWROK,
.gpio7 = GPIO_RESET_PWROK,
.gpio8 = GPIO_RESET_PWROK,
.gpio9 = GPIO_RESET_PWROK,
.gpio10 = GPIO_RESET_PWROK,
.gpio11 = GPIO_RESET_PWROK,
.gpio12 = GPIO_RESET_PWROK,
.gpio13 = GPIO_RESET_PWROK,
.gpio14 = GPIO_RESET_PWROK,
.gpio15 = GPIO_RESET_PWROK,
.gpio16 = GPIO_RESET_PWROK,
.gpio17 = GPIO_RESET_PWROK,
.gpio18 = GPIO_RESET_PWROK,
.gpio19 = GPIO_RESET_PWROK,
.gpio20 = GPIO_RESET_PWROK,
.gpio21 = GPIO_RESET_PWROK,
.gpio22 = GPIO_RESET_PWROK,
.gpio23 = GPIO_RESET_PWROK,
.gpio24 = GPIO_RESET_RSMRST,
.gpio25 = GPIO_RESET_PWROK,
.gpio26 = GPIO_RESET_PWROK,
.gpio27 = GPIO_RESET_PWROK,
.gpio28 = GPIO_RESET_PWROK,
.gpio29 = GPIO_RESET_PWROK,
.gpio30 = GPIO_RESET_PWROK,
.gpio31 = GPIO_RESET_PWROK,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_NO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio2 = GPIO_NO_INVERT,
.gpio3 = GPIO_NO_INVERT,
.gpio4 = GPIO_INVERT,
.gpio5 = GPIO_INVERT,
.gpio6 = GPIO_NO_INVERT,
.gpio7 = GPIO_INVERT,
.gpio8 = GPIO_NO_INVERT,
.gpio9 = GPIO_INVERT,
.gpio10 = GPIO_NO_INVERT,
.gpio11 = GPIO_NO_INVERT,
.gpio12 = GPIO_NO_INVERT,
.gpio13 = GPIO_NO_INVERT,
.gpio14 = GPIO_NO_INVERT,
.gpio15 = GPIO_NO_INVERT,
.gpio16 = GPIO_NO_INVERT,
.gpio17 = GPIO_NO_INVERT,
.gpio18 = GPIO_NO_INVERT,
.gpio19 = GPIO_NO_INVERT,
.gpio20 = GPIO_NO_INVERT,
.gpio21 = GPIO_NO_INVERT,
.gpio22 = GPIO_NO_INVERT,
.gpio23 = GPIO_NO_INVERT,
.gpio24 = GPIO_NO_INVERT,
.gpio25 = GPIO_NO_INVERT,
.gpio26 = GPIO_NO_INVERT,
.gpio27 = GPIO_NO_INVERT,
.gpio28 = GPIO_NO_INVERT,
.gpio29 = GPIO_NO_INVERT,
.gpio30 = GPIO_NO_INVERT,
.gpio31 = GPIO_NO_INVERT,
};
const struct pch_gpio_set1 pch_gpio_set1_blink = {
.gpio0 = GPIO_NO_BLINK,
.gpio1 = GPIO_NO_BLINK,
.gpio2 = GPIO_NO_BLINK,
.gpio3 = GPIO_NO_BLINK,
.gpio4 = GPIO_NO_BLINK,
.gpio5 = GPIO_NO_BLINK,
.gpio6 = GPIO_NO_BLINK,
.gpio7 = GPIO_NO_BLINK,
.gpio8 = GPIO_NO_BLINK,
.gpio9 = GPIO_NO_BLINK,
.gpio10 = GPIO_NO_BLINK,
.gpio11 = GPIO_NO_BLINK,
.gpio12 = GPIO_NO_BLINK,
.gpio13 = GPIO_NO_BLINK,
.gpio14 = GPIO_NO_BLINK,
.gpio15 = GPIO_NO_BLINK,
.gpio16 = GPIO_NO_BLINK,
.gpio17 = GPIO_NO_BLINK,
.gpio18 = GPIO_NO_BLINK,
.gpio19 = GPIO_NO_BLINK,
.gpio20 = GPIO_NO_BLINK,
.gpio21 = GPIO_NO_BLINK,
.gpio22 = GPIO_NO_BLINK,
.gpio23 = GPIO_NO_BLINK,
.gpio24 = GPIO_NO_BLINK,
.gpio25 = GPIO_NO_BLINK,
.gpio26 = GPIO_NO_BLINK,
.gpio27 = GPIO_NO_BLINK,
.gpio28 = GPIO_NO_BLINK,
.gpio29 = GPIO_NO_BLINK,
.gpio30 = GPIO_NO_BLINK,
.gpio31 = GPIO_NO_BLINK,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio40 = GPIO_MODE_GPIO,
.gpio41 = GPIO_MODE_GPIO,
.gpio42 = GPIO_MODE_GPIO,
.gpio43 = GPIO_MODE_GPIO,
.gpio44 = GPIO_MODE_GPIO,
.gpio45 = GPIO_MODE_GPIO,
.gpio46 = GPIO_MODE_GPIO,
.gpio47 = GPIO_MODE_GPIO,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio50 = GPIO_MODE_GPIO,
.gpio51 = GPIO_MODE_GPIO,
.gpio52 = GPIO_MODE_GPIO,
.gpio53 = GPIO_MODE_GPIO,
.gpio54 = GPIO_MODE_GPIO,
.gpio55 = GPIO_MODE_GPIO,
.gpio56 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
.gpio58 = GPIO_MODE_NATIVE,
.gpio59 = GPIO_MODE_GPIO,
.gpio60 = GPIO_MODE_GPIO,
.gpio61 = GPIO_MODE_NATIVE,
.gpio62 = GPIO_MODE_NATIVE,
.gpio63 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_OUTPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_OUTPUT,
.gpio35 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_OUTPUT,
.gpio38 = GPIO_DIR_OUTPUT,
.gpio39 = GPIO_DIR_OUTPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_INPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio53 = GPIO_DIR_INPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_INPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio58 = GPIO_DIR_INPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
.gpio61 = GPIO_DIR_OUTPUT,
.gpio62 = GPIO_DIR_OUTPUT,
.gpio63 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_LOW,
.gpio33 = GPIO_LEVEL_LOW,
.gpio34 = GPIO_LEVEL_HIGH,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_LOW,
.gpio37 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_LOW,
.gpio39 = GPIO_LEVEL_LOW,
.gpio40 = GPIO_LEVEL_HIGH,
.gpio41 = GPIO_LEVEL_LOW,
.gpio42 = GPIO_LEVEL_HIGH,
.gpio43 = GPIO_LEVEL_HIGH,
.gpio44 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_LOW,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio47 = GPIO_LEVEL_HIGH,
.gpio48 = GPIO_LEVEL_HIGH,
.gpio49 = GPIO_LEVEL_LOW,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_LOW,
.gpio52 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_LOW,
.gpio54 = GPIO_LEVEL_HIGH,
.gpio55 = GPIO_LEVEL_LOW,
.gpio56 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_HIGH,
.gpio58 = GPIO_LEVEL_HIGH,
.gpio59 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio61 = GPIO_LEVEL_HIGH,
.gpio62 = GPIO_LEVEL_HIGH,
.gpio63 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set2 pch_gpio_set2_reset = {
.gpio32 = GPIO_RESET_PWROK,
.gpio33 = GPIO_RESET_PWROK,
.gpio34 = GPIO_RESET_PWROK,
.gpio35 = GPIO_RESET_PWROK,
.gpio36 = GPIO_RESET_PWROK,
.gpio37 = GPIO_RESET_PWROK,
.gpio38 = GPIO_RESET_PWROK,
.gpio39 = GPIO_RESET_PWROK,
.gpio40 = GPIO_RESET_PWROK,
.gpio41 = GPIO_RESET_PWROK,
.gpio42 = GPIO_RESET_PWROK,
.gpio43 = GPIO_RESET_PWROK,
.gpio44 = GPIO_RESET_PWROK,
.gpio45 = GPIO_RESET_PWROK,
.gpio46 = GPIO_RESET_PWROK,
.gpio47 = GPIO_RESET_PWROK,
.gpio48 = GPIO_RESET_PWROK,
.gpio49 = GPIO_RESET_PWROK,
.gpio50 = GPIO_RESET_PWROK,
.gpio51 = GPIO_RESET_PWROK,
.gpio52 = GPIO_RESET_PWROK,
.gpio53 = GPIO_RESET_PWROK,
.gpio54 = GPIO_RESET_PWROK,
.gpio55 = GPIO_RESET_PWROK,
.gpio56 = GPIO_RESET_PWROK,
.gpio57 = GPIO_RESET_PWROK,
.gpio58 = GPIO_RESET_PWROK,
.gpio59 = GPIO_RESET_PWROK,
.gpio60 = GPIO_RESET_PWROK,
.gpio61 = GPIO_RESET_PWROK,
.gpio62 = GPIO_RESET_PWROK,
.gpio63 = GPIO_RESET_PWROK,
};
const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_GPIO,
.gpio65 = GPIO_MODE_GPIO,
.gpio66 = GPIO_MODE_GPIO,
.gpio67 = GPIO_MODE_GPIO,
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio70 = GPIO_MODE_GPIO,
.gpio71 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_NATIVE,
.gpio73 = GPIO_MODE_GPIO,
.gpio74 = GPIO_MODE_GPIO,
.gpio75 = GPIO_MODE_NATIVE,
};
const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio64 = GPIO_DIR_INPUT,
.gpio65 = GPIO_DIR_INPUT,
.gpio66 = GPIO_DIR_INPUT,
.gpio67 = GPIO_DIR_INPUT,
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
.gpio75 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio64 = GPIO_LEVEL_LOW,
.gpio65 = GPIO_LEVEL_LOW,
.gpio66 = GPIO_LEVEL_LOW,
.gpio67 = GPIO_LEVEL_LOW,
.gpio68 = GPIO_LEVEL_LOW,
.gpio69 = GPIO_LEVEL_HIGH,
.gpio70 = GPIO_LEVEL_HIGH,
.gpio71 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_HIGH,
.gpio73 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
.gpio75 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set3 pch_gpio_set3_reset = {
.gpio64 = GPIO_RESET_PWROK,
.gpio65 = GPIO_RESET_PWROK,
.gpio66 = GPIO_RESET_PWROK,
.gpio67 = GPIO_RESET_PWROK,
.gpio68 = GPIO_RESET_PWROK,
.gpio69 = GPIO_RESET_PWROK,
.gpio70 = GPIO_RESET_PWROK,
.gpio71 = GPIO_RESET_PWROK,
.gpio72 = GPIO_RESET_PWROK,
.gpio73 = GPIO_RESET_PWROK,
.gpio74 = GPIO_RESET_PWROK,
.gpio75 = GPIO_RESET_PWROK,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

59
src/mainboard/apple/macbookair4_2/hda_verb.c Normal file
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#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10134206, /* Codec Vendor / Device ID: Cirrus */
0x106b5b00, /* Subsystem ID */
0x0000000b, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x0, 0x106b5b00),
/* NID 0x09. */
AZALIA_PIN_CFG(0x0, 0x09, 0x012b4030),
/* NID 0x0a. */
AZALIA_PIN_CFG(0x0, 0x0a, 0x400000f0),
/* NID 0x0b. */
AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120),
/* NID 0x0c. */
AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0),
/* NID 0x0d. */
AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110),
/* NID 0x0e. */
AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0),
/* NID 0x0f. */
AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0),
/* NID 0x10. */
AZALIA_PIN_CFG(0x0, 0x10, 0x400000f0),
/* NID 0x12. */
AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0),
/* NID 0x15. */
AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0),
0x80862805, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
0x00000004, /* Number of 4 dword sets */
/* NID 0x01: Subsystem ID. */
AZALIA_SUBVENDOR(0x3, 0x80860101),
/* NID 0x05. */
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
/* NID 0x06. */
AZALIA_PIN_CFG(0x3, 0x06, 0x18560010),
/* NID 0x07. */
AZALIA_PIN_CFG(0x3, 0x07, 0x18560010),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

51
src/mainboard/apple/macbookair4_2/mainboard.c Normal file
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#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/acpi/ec.h>
#include <console/console.h>
static void mainboard_init(device_t dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00800000;
RCBA32(0x38c0) = 0x00000007;
/* FIXME: trim this down or remove if necessary */
{
int i;
const u8 dmp[256] = {
/* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
/* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
printk(BIOS_DEBUG, "Replaying EC dump ...");
for (i = 0; i < 256; i++)
ec_write (i, dmp[i]);
printk(BIOS_DEBUG, "done\n");
}
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
/* FIXME: fix those values*/
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

1
src/mainboard/apple/macbookair4_2/romstage.c Normal file
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/* dummy file */