sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

lenovo/t420s: Add new port.

Browse Source 
This is based on x220 and t520. Tested on i7 model with usb3.
There is no support for nvidia gpu and optimus.

Change-Id: I6ca9436ccec3024095d02078e5e450147841e463
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Nicolas Reinecke
2014-12-29 19:57:29 +01:00
committed by Peter Stuge
parent c619c41890
commit 572795bf08
18 changed files with 1435 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/lenovo/Kconfig
View File

@@ -32,6 +32,11 @@ config BOARD_LENOVO_X230
help
Lenovo X230 laptop. Consult wiki for details.
config BOARD_LENOVO_T420S
bool "ThinkPad T420s"
help
Lenovo T420s laptop. Consult wiki for details.
config BOARD_LENOVO_T520
bool "ThinkPad T520"
help
@@ -62,6 +67,7 @@ source "src/mainboard/lenovo/x200/Kconfig"
source "src/mainboard/lenovo/x201/Kconfig"
source "src/mainboard/lenovo/x220/Kconfig"
source "src/mainboard/lenovo/x230/Kconfig"
source "src/mainboard/lenovo/t420s/Kconfig"
source "src/mainboard/lenovo/t520/Kconfig"
source "src/mainboard/lenovo/t530/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"

74
src/mainboard/lenovo/t420s/Kconfig Normal file
View File

@@ -0,0 +1,74 @@
if BOARD_LENOVO_T420S
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_RPGA988B
select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
select SOUTHBRIDGE_INTEL_BD82X6X
select EC_LENOVO_PMH7
select EC_LENOVO_H8
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_INT15
select VGA
select INTEL_EDID
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select SANDYBRIDGE_LVDS
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default lenovo/t420s
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T420s"
config MMCONF_BASE_ADDRESS
hex
default 0xf0000000
config MAX_CPUS
int
default 8
config USBDEBUG_HCD_INDEX
int
default 2
config DRAM_RESET_GATE_GPIO
int
default 10
config VGA_BIOS_FILE
string
default "pci8086,0126.rom"
config VGA_BIOS_ID
string
default "8086,0126"
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x17aa
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x21d2
endif # BOARD_LENOVO_T420S

21
src/mainboard/lenovo/t420s/Makefile.inc Normal file
View File

@@ -0,0 +1,21 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += gpio.c

26
src/mainboard/lenovo/t420s/acpi/ec.asl Normal file
View File

@@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <ec/lenovo/h8/acpi/ec.asl>
Scope(\_SB.PCI0.LPCB.EC)
{
}

77
src/mainboard/lenovo/t420s/acpi/platform.asl Normal file
View File

@@ -0,0 +1,77 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (POST, SystemIO, 0x80, 1)
Field (POST, ByteAcc, Lock, Preserve)
{
DBG0, 8
}
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method(_PIC, 1)
{
// Remember the OS' IRQ routing choice.
Store(Arg0, PICM)
}
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method(_PTS,1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
/* ME may not be up yet. */
Store (0, \_TZ.MEB1)
Store (0, \_TZ.MEB2)
/* Not implemented. */
Return(Package(){0,0})
}

1
src/mainboard/lenovo/t420s/acpi/superio.asl Normal file
View File

@@ -0,0 +1 @@
#include <drivers/pc80/ps2_controller.asl>

78
src/mainboard/lenovo/t420s/acpi_tables.c Normal file
View File

@@ -0,0 +1,78 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <arch/acpigen.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
static void acpi_update_thermal_table(global_nvs_t *gnvs)
{
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
}
void acpi_create_gnvs(global_nvs_t *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
gnvs->s3u1 = 0;
/* Disable USB ports in S5 by default */
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
/* IGD Displays */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[2] = 0x80000410;
gnvs->did[3] = 0x80000410;
gnvs->did[4] = 0x00000005;
// the lid is open by default.
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
}
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
return current;
}
unsigned long acpi_fill_srat(unsigned long current)
{
/* No NUMA, no SRAT */
return current;
}

5
src/mainboard/lenovo/t420s/board_info.txt Normal file
View File

@@ -0,0 +1,5 @@
Category: laptop
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: n

17
src/mainboard/lenovo/t420s/cmos.default Normal file
View File

@@ -0,0 +1,17 @@
boot_option=Fallback
last_boot=Fallback
baud_rate=115200
debug_level=Spew
power_on_after_fail=Enable
nmi=Enable
volume=0x3
first_battery=Primary
bluetooth=Enable
wwan=Enable
wlan=Enable
touchpad=Enable
sata_mode=AHCI
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
hyper_threading=Enable

167
src/mainboard/lenovo/t420s/cmos.layout Normal file
View File

@@ -0,0 +1,167 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
## Copyright (C) 2014 Vladimir Serbinenko
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
388 4 r 0 reboot_bits
#390 2 r 0 unused?
# -----------------------------------------------------------------
# coreboot config options: console
392 3 e 5 baud_rate
395 4 e 6 debug_level
#399 1 r 0 unused
400 8 h 0 volume
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: EC
411 1 e 8 first_battery
412 1 e 1 bluetooth
413 1 e 1 wwan
414 1 e 1 touchpad
415 1 e 1 wlan
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
418 1 e 1 sticky_fn
419 1 e 1 power_management_beeps
421 1 e 9 sata_mode
#422 2 r 1 unused
# coreboot config options: cpu
424 1 e 2 hyper_threading
#425 7 r 0 unused
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
#435 549 r 0 unused
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 Secondary
8 1 Primary
9 0 AHCI
9 1 Compatible
10 0 Both
10 1 Keyboard only
10 2 Thinklight only
10 3 None
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums
checksum 392 415 984

172
src/mainboard/lenovo/t420s/devicetree.cb Normal file
View File

@@ -0,0 +1,172 @@
chip northbridge/intel/sandybridge
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_power_cycle_delay" = "1"
register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gfx.use_spread_spectrum_clock" = "1"
register "gfx.lvds_dual_channel" = "1"
register "gfx.link_frequency_270_mhz" = "1"
register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610"
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA988B
device lapic 0 on end
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
# Coordinate with HW_ALL
register "pstate_coord_type" = "0xfe"
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device domain 0 on
device pci 00.0 on
subsystemid 0x17aa 0x21d2
end # host bridge
device pci 01.0 off end # NVIDIA Corporation GF119M [NVS 4200M]
device pci 02.0 on
subsystemid 0x17aa 0x21d3
end # Integrated Graphics Controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
register "gpi8_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
register "sata_port_map" = "0x17"
# Set max SATA speed to 6.0 Gb/s
register "sata_interface_speed_support" = "0x3"
register "gen1_dec" = "0x7c1601"
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
register "p_cnt_throttling_supported" = "1"
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 on
subsystemid 0x17aa 0x21ce
end # Intel Gigabit Ethernet
device pci 1a.0 on
subsystemid 0x17aa 0x21d2
end # USB Enhanced Host Controller #2
device pci 1b.0 on
subsystemid 0x17aa 0x21d2
end # High Definition Audio Controller
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 on
subsystemid 0x17aa 0x21d2
end # PCIe Port #2 Integrated Wireless LAN
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on
subsystemid 0x17aa 0x21d2
end # PCIe Port #4 ExpressCard
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
device pci 1c.6 on
subsystemid 0x17aa 0x21d2
end # PCIe Port #7 NEC Corporation uPD720200A USB 3.0 Host Controller
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on
subsystemid 0x17aa 0x21d2
end # USB Enhanced Host Controller #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
subsystemid 0x17aa 0x21d2
chip ec/lenovo/pmh7
device pnp ff.1 on # dummy
end
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62
io 0x62 = 0x66
io 0x64 = 0x1600
io 0x66 = 0x1604
end
register "config0" = "0xa7"
register "config1" = "0x01"
register "config2" = "0xa0"
register "config3" = "0xe2"
register "has_keyboard_backlight" = "0"
register "beepmask0" = "0x02"
register "beepmask1" = "0x86"
register "has_power_management_beeps" = "1"
register "event2_enable" = "0xff"
register "event3_enable" = "0xff"
register "event4_enable" = "0xf0"
register "event5_enable" = "0x3c"
register "event6_enable" = "0x00"
register "event7_enable" = "0xa1"
register "event8_enable" = "0x7b"
register "event9_enable" = "0xff"
register "eventa_enable" = "0x00"
register "eventb_enable" = "0x00"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
end
end # LPC Controller
device pci 1f.2 on
subsystemid 0x17aa 0x21d2
end # 6 port SATA AHCI Controller
device pci 1f.3 on
subsystemid 0x17aa 0x21d2
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
device i2c 55 on end
device i2c 56 on end
device i2c 57 on end
device i2c 5c on end
device i2c 5d on end
device i2c 5e on end
device i2c 5f on end
end
end # SMBus Controller
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on
subsystemid 0x17aa 0x21d2
end # Thermal
end
end
end

56
src/mainboard/lenovo/t420s/dsdt.asl Normal file
View File

@@ -0,0 +1,56 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define THINKPAD_EC_GPE 17
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
#define HAVE_LCD_SCREEN 1
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0
"COREv4", // OEM id
"COREBOOT", // OEM table id
0x20110725 // OEM revision
)
{
// Some generic macros
#include "acpi/platform.asl"
// global NVS and variables
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <cpu/intel/model_206ax/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

285
src/mainboard/lenovo/t420s/gpio.c Normal file
View File

@@ -0,0 +1,285 @@
#include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, // -USB30_SMIB - input
.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
.gpio2 = GPIO_MODE_GPIO, // -LCD_PRESENCE - input
.gpio3 = GPIO_MODE_GPIO, // DOCKID0 - input
.gpio4 = GPIO_MODE_GPIO, // DOCKID1 - input
.gpio5 = GPIO_MODE_GPIO, // DOCKID2 - input
.gpio6 = GPIO_MODE_GPIO, // SYSTEM_DP_HPD - input
.gpio7 = GPIO_MODE_GPIO, // pullup
.gpio8 = GPIO_MODE_GPIO, // pulldown - INTEGRATED ENABLED(FCIM) 0 / DISABLED (BTM) 1
.gpio9 = GPIO_MODE_NATIVE, // OC5 - -USB_PORT9_OC5 - input
.gpio10 = GPIO_MODE_GPIO, // DRAMRST_GATE_ON - output
.gpio11 = GPIO_MODE_NATIVE, // SMBALERT# pullup
.gpio12 = GPIO_MODE_NATIVE, // LANPHYPC - output
.gpio13 = GPIO_MODE_GPIO, // -EC_WAKE - input
.gpio14 = GPIO_MODE_NATIVE, // OC7 - pullup
.gpio15 = GPIO_MODE_GPIO, // pullup - ME CRYPTO STRAP WITH TLS CONFIDENTIALITY
.gpio16 = GPIO_MODE_NATIVE, // SATA4GP - SATA_DOCK_DTCT - input from gpio33
.gpio17 = GPIO_MODE_GPIO, // DGFX_PW RGD - input
.gpio18 = GPIO_MODE_NATIVE, // PCIECLKRQ1 - -CLKREQ_WLAN - input
.gpio19 = GPIO_MODE_NATIVE, // SATA1GP - SATA_BAY_DTCT - input to gpio22
.gpio20 = GPIO_MODE_NATIVE, // PCIECLKRQ2 - pullup
.gpio21 = GPIO_MODE_GPIO, // -DISCRETE_GFX_PRESENCE - input
.gpio22 = GPIO_MODE_GPIO, // SATA_BAY_DTCT - output to SATA1GP
.gpio23 = GPIO_MODE_NATIVE, // LDRQ1 - TP84
.gpio24 = GPIO_MODE_GPIO, // pullup
.gpio25 = GPIO_MODE_NATIVE, // PCIECLKRQ3 - -CLKREQ_EXC - input
.gpio26 = GPIO_MODE_NATIVE, // PCIECLKRQ4 - pullup
.gpio27 = GPIO_MODE_GPIO, // -MSATA_DTCT - input
.gpio28 = GPIO_MODE_GPIO, // pulldown possible
.gpio29 = GPIO_MODE_GPIO, // SLP_LAN - -PCH_SLP_LAN
.gpio30 = GPIO_MODE_NATIVE, // SUSPWRDNACK - output
.gpio31 = GPIO_MODE_NATIVE, // ACPRESENT - input
};
const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio1 = GPIO_DIR_INPUT,
.gpio2 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio4 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio6 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_OUTPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_OUTPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_INPUT,
.gpio17 = GPIO_DIR_INPUT,
.gpio18 = GPIO_DIR_INPUT,
.gpio19 = GPIO_DIR_INPUT,
.gpio20 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio22 = GPIO_DIR_OUTPUT,
.gpio23 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_INPUT,
.gpio26 = GPIO_DIR_INPUT,
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_OUTPUT,
.gpio29 = GPIO_DIR_OUTPUT,
.gpio30 = GPIO_DIR_OUTPUT,
.gpio31 = GPIO_DIR_INPUT
};
const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_LOW,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_LOW,
.gpio7 = GPIO_LEVEL_HIGH,
.gpio8 = GPIO_LEVEL_HIGH,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_HIGH,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_LOW,
.gpio19 = GPIO_LEVEL_HIGH,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio21 = GPIO_LEVEL_LOW,
.gpio22 = GPIO_LEVEL_HIGH,
.gpio23 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
.gpio25 = GPIO_LEVEL_LOW,
.gpio26 = GPIO_LEVEL_HIGH,
.gpio27 = GPIO_LEVEL_HIGH,
.gpio28 = GPIO_LEVEL_LOW,
.gpio29 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
.gpio31 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio1 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
const struct pch_gpio_set1 pch_gpio_set1_blink = {
.gpio18 = GPIO_NO_BLINK,
};
const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_NATIVE, // CLKRUN - output
.gpio33 = GPIO_MODE_GPIO, // SATA_DOCK_DTCT - output to SATA4GP
.gpio34 = GPIO_MODE_GPIO, // DGFX_VRM_ID - input - HIGH: 1GB / LOW: 2GB
.gpio35 = GPIO_MODE_GPIO, // pullup
.gpio36 = GPIO_MODE_GPIO, // pulldown
.gpio37 = GPIO_MODE_GPIO, // pulldown
.gpio38 = GPIO_MODE_GPIO, // planarid2 - input - pulldown
.gpio39 = GPIO_MODE_GPIO, // planarid3 - input - pulldown
.gpio40 = GPIO_MODE_NATIVE, // OC1 - -USB_PORT1_OC1 - input
.gpio41 = GPIO_MODE_NATIVE, // OC2 - pullup
.gpio42 = GPIO_MODE_GPIO, // SMB_3B_EN - output
.gpio43 = GPIO_MODE_NATIVE, // OC4 - pullup
.gpio44 = GPIO_MODE_NATIVE, // PCIECLKRQ5 - -CLKREQ_GBE - input
.gpio45 = GPIO_MODE_NATIVE, // PCIECLKRQ6 - -CLKREQ_USB30_TR - input
.gpio46 = GPIO_MODE_NATIVE, // PCIECLKRQ7 - pullup
.gpio47 = GPIO_MODE_NATIVE, // PEG_A_CLKRQ# - input
.gpio48 = GPIO_MODE_GPIO, // planarid0 - input - PDV low / FVT high
.gpio49 = GPIO_MODE_GPIO, // planarid1 - input - pulldown
.gpio50 = GPIO_MODE_GPIO, // -SC_DTCT - input
.gpio51 = GPIO_MODE_GPIO, // pullup
.gpio52 = GPIO_MODE_GPIO, // OPTIMUS_ENABLE - output - high: igpu / low: dgpu
.gpio53 = GPIO_MODE_GPIO, // pullup
.gpio54 = GPIO_MODE_GPIO, // -BDC_PRESENCE - input
.gpio55 = GPIO_MODE_GPIO, // pullup
.gpio56 = GPIO_MODE_NATIVE, // PEG_B_CLKRQ - pullup
.gpio57 = GPIO_MODE_GPIO, // -DTPM_PRESENCE - input
.gpio58 = GPIO_MODE_NATIVE, // SML1CLK - EC_SCL2 - output
.gpio59 = GPIO_MODE_NATIVE, // OC0 - pullup
.gpio60 = GPIO_MODE_NATIVE, // SML0ALERT# - pullup
.gpio61 = GPIO_MODE_NATIVE, // SUS_STAT - output
.gpio62 = GPIO_MODE_NATIVE, // SUSCLK - output
.gpio63 = GPIO_MODE_NATIVE, // SLP_S5 - output
};
const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio32 = GPIO_DIR_INPUT,
.gpio33 = GPIO_DIR_OUTPUT,
.gpio34 = GPIO_DIR_INPUT,
.gpio35 = GPIO_DIR_OUTPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_OUTPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio51 = GPIO_DIR_OUTPUT,
.gpio52 = GPIO_DIR_OUTPUT,
.gpio53 = GPIO_DIR_OUTPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio55 = GPIO_DIR_OUTPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio58 = GPIO_DIR_INPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
.gpio61 = GPIO_DIR_OUTPUT,
.gpio62 = GPIO_DIR_OUTPUT,
.gpio63 = GPIO_DIR_OUTPUT,
};
const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio32 = GPIO_LEVEL_HIGH,
.gpio33 = GPIO_LEVEL_HIGH,
.gpio34 = GPIO_LEVEL_HIGH,
.gpio35 = GPIO_LEVEL_LOW,
.gpio36 = GPIO_LEVEL_LOW,
.gpio37 = GPIO_LEVEL_LOW,
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_LOW,
.gpio40 = GPIO_LEVEL_HIGH,
.gpio41 = GPIO_LEVEL_HIGH,
.gpio42 = GPIO_LEVEL_HIGH,
.gpio43 = GPIO_LEVEL_HIGH,
.gpio44 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_LOW,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio47 = GPIO_LEVEL_LOW,
.gpio48 = GPIO_LEVEL_HIGH,
.gpio49 = GPIO_LEVEL_HIGH,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio51 = GPIO_LEVEL_HIGH,
.gpio52 = GPIO_LEVEL_HIGH,
.gpio53 = GPIO_LEVEL_HIGH,
.gpio54 = GPIO_LEVEL_LOW,
.gpio55 = GPIO_LEVEL_HIGH,
.gpio56 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_LOW,
.gpio58 = GPIO_LEVEL_HIGH,
.gpio59 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio61 = GPIO_LEVEL_HIGH,
.gpio62 = GPIO_LEVEL_LOW,
.gpio63 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio64 = GPIO_MODE_NATIVE, // NC
.gpio65 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_NSS - output
.gpio66 = GPIO_MODE_NATIVE, // NC
.gpio67 = GPIO_MODE_NATIVE, // VIDEO_CLK_27M_SS - output
.gpio68 = GPIO_MODE_GPIO, // -INT_MIC_DTCT - input
.gpio69 = GPIO_MODE_GPIO, // mic enable bit - low enable - pulldown
.gpio70 = GPIO_MODE_GPIO, // pullup
.gpio71 = GPIO_MODE_GPIO, // pullup
.gpio72 = GPIO_MODE_NATIVE, // BATLOW - input
.gpio73 = GPIO_MODE_NATIVE, // pullup
.gpio74 = GPIO_MODE_NATIVE, // pullup
.gpio75 = GPIO_MODE_NATIVE, // SML1DATA - EC_SDA2 - i/o
};
const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio64 = GPIO_DIR_OUTPUT,
.gpio65 = GPIO_DIR_OUTPUT,
.gpio66 = GPIO_DIR_OUTPUT,
.gpio67 = GPIO_DIR_OUTPUT,
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
.gpio75 = GPIO_DIR_INPUT,
};
const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio64 = GPIO_LEVEL_HIGH,
.gpio65 = GPIO_LEVEL_HIGH,
.gpio66 = GPIO_LEVEL_HIGH,
.gpio67 = GPIO_LEVEL_HIGH,
.gpio68 = GPIO_LEVEL_LOW,
.gpio69 = GPIO_LEVEL_LOW,
.gpio70 = GPIO_LEVEL_LOW,
.gpio71 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_HIGH,
.gpio73 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
.gpio75 = GPIO_LEVEL_HIGH,
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
.blink = &pch_gpio_set1_blink,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};

73
src/mainboard/lenovo/t420s/hda_verb.c Normal file
View File

@@ -0,0 +1,73 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Vendor Name : Conexant
* Vendor ID : 0x14f1506e
* Subsystem ID : 0x17aa21d2
* Revision ID : 0x100002
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic show CX20672
0x17aa21d2, // Subsystem ID
0x0000000d, // Number of 4 dword sets
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01 - NodeInfo */
AZALIA_SUBVENDOR(0x0, 0x17AA21D2),
AZALIA_PIN_CFG(0x0, 0x19, 0x04211040),
AZALIA_PIN_CFG(0x0, 0x1A, 0x61A19050),
AZALIA_PIN_CFG(0x0, 0x1B, 0x04A11060),
AZALIA_PIN_CFG(0x0, 0x1C, 0x6121401F),
AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0),
AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0),
AZALIA_PIN_CFG(0x0, 0x1F, 0x90170110),
AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0),
AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0),
AZALIA_PIN_CFG(0x0, 0x23, 0x90A60170),
/* Misc entries */
0x00B707C0, /* Enable PortB as Output with HP amp */
0x00D70740, /* Enable PortD as Output */
0x0017A200, /* Disable ClkEn of PortSenseTst */
0x0017C621, /* Slave Port - Port A used as microphone input for
combo Jack
Master Port - Port B used for Jack Presence Detect
Enable Combo Jack Detection */
0x0017A208, /* Enable ClkEn of PortSenseTst */
0x00170500, /* Set power state to D0 */
0x00170500, /* Padding */
0x00170500, /* Padding */
};
const u32 pc_beep_verbs[] = {
0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
};
AZALIA_ARRAY_SIZES;

80
src/mainboard/lenovo/t420s/mainboard.c Normal file
View File

@@ -0,0 +1,80 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2011-2012 Google Inc.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
#include <string.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h>
#include <arch/acpi.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#include <device/pci.h>
#include <pc80/keyboard.h>
#include <ec/lenovo/h8/h8.h>
#include <version.h>
void mainboard_suspend_resume(void)
{
/* Call SMM finalize() handlers before resume */
outb(0xcb, 0xb2);
}
const char *smbios_mainboard_bios_version(void)
{
static char *s = NULL;
/* Satisfy thinkpad_acpi. */
if (strlen(CONFIG_LOCALVERSION))
return "CBET4000 " CONFIG_LOCALVERSION;
if (s != NULL)
return s;
s = strconcat("CBET4000 ", coreboot_version);
return s;
}
static void mainboard_init(device_t dev)
{
/* init spi */
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
RCBA32(0x38c0) = 0x00000007;
pc_keyboard_init();
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
void h8_mainboard_init_dock(void)
{
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

73
src/mainboard/lenovo/t420s/romstage.c Normal file
View File

@@ -0,0 +1,73 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/byteorder.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
void pch_enable_lpc(void)
{
/* EC Decode Range Port60/64, Port62/66 */
/* Enable EC, PS/2 Keyboard/Mouse */
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN);
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
}
void rcba_config(void)
{
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x1eb51fe3;
RCBA32(BUC) = 0;
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 1, -1 }, /* P0 empty */
{ 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */
{ 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */
{ 1, 0, -1 }, /* P3: WWAN, no OC */
{ 1, 1, -1 }, /* P4: smartcard, no OC */
{ 1, 1, -1 }, /* P5: ExpressCard, no OC */
{ 0, 0, -1 }, /* P6: empty */
{ 0, 0, -1 }, /* P7: empty */
{ 0, 1, -1 }, /* P8: empty (touch panel) */
{ 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */
{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
{ 1, 1, -1 }, /* P12: docking, no OC */
{ 1, 1, -1 }, /* P13: camera (LCD), no OC */
};
void mainboard_get_spd(spd_raw_data *spd) {
read_spd(&spd[0], 0x50);
read_spd(&spd[2], 0x51);
}

194
src/mainboard/lenovo/t420s/smihandler.c Normal file
View File

@@ -0,0 +1,194 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h>
#include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
extern global_nvs_t *gnvs;
static void mainboard_smm_init(void)
{
printk(BIOS_DEBUG, "initializing SMI\n");
/* Enable 0x1600/0x1600 register pair */
ec_set_bit(0x00, 0x05);
}
int mainboard_io_trap_handler(int smif)
{
static int smm_initialized;
if (!smm_initialized) {
mainboard_smm_init();
smm_initialized = 1;
}
switch (smif) {
default:
return 0;
}
/* On success, the IO Trap Handler returns 1
* On failure, the IO Trap Handler returns a value != 1 */
return 1;
}
static void mainboard_smi_brightness_up(void)
{
u8 value;
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
}
static void mainboard_smi_brightness_down(void)
{
u8 value;
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
(value - 0x10) & 0xf0);
}
static void mainboard_smi_handle_ec_sci(void)
{
u8 status = inb(EC_SC);
u8 event;
if (!(status & EC_SCI_EVT))
return;
event = ec_query();
printk(BIOS_DEBUG, "EC event %02x\n", event);
switch (event) {
case 0x14:
/* brightness up */
mainboard_smi_brightness_up();
break;
case 0x15:
/* brightness down */
mainboard_smi_brightness_down();
break;
default:
break;
}
}
void mainboard_smi_gpi(u32 gpi_sts)
{
if (gpi_sts & (1 << 12))
mainboard_smi_handle_ec_sci();
}
static int mainboard_finalized = 0;
int mainboard_smi_apmc(u8 data)
{
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
u8 tmp;
printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
data);
if (!pmbase)
return 0;
switch (data) {
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
/* route H8SCI to SCI */
outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
case APM_CNT_ACPI_DISABLE:
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
/* route H8SCI# to SMI */
outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x01;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
/* discard all events, and enable attention */
ec_write(0x80, 0x01);
break;
case APM_CNT_FINALIZE:
printk(BIOS_DEBUG, "APMC: FINALIZE\n");
if (mainboard_finalized) {
printk(BIOS_DEBUG, "APMC#: Already finalized\n");
return 0;
}
intel_me_finalize_smm();
intel_pch_finalize_smm();
intel_sandybridge_finalize_smm();
intel_model_206ax_finalize_smm();
mainboard_finalized = 1;
break;
default:
break;
}
return 0;
}
void mainboard_smi_sleep(u8 slp_typ)
{
if (slp_typ == 3) {
u8 ec_wake = ec_read(0x32);
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
if (ec_wake & 0x14) {
u32 gpe_rout;
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
gpe_rout &= ~(3 << 26);
gpe_rout |= (2 << 26);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
}

30
src/mainboard/lenovo/t420s/thermal.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef T420S_THERMAL_H
#define T420S_THERMAL_H
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 100
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
#endif