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skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope

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Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83189
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2024-06-23 21:39:55 +02:00
parent 4b72203989
commit 576f1cd44b
4 changed files with 8 additions and 14 deletions
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6
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
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@@ -41,10 +41,6 @@ chip soc/intel/skylake
# RP17, uses CLK SRC 7 # RP17, uses CLK SRC 7
register "PcieRpClkSrcNumber[16]" = "7" register "PcieRpClkSrcNumber[16]" = "7"
# USB related
register "SsicPortEnable" = "1"
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -66,6 +62,8 @@ chip soc/intel/skylake
device domain 0 on device domain 0 on
device ref south_xhci on device ref south_xhci on
register "SsicPortEnable" = "1"
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */

5
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
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@@ -71,9 +71,6 @@ chip soc/intel/skylake
# RP10, uses CLK SRC 4 # RP10, uses CLK SRC 4
register "PcieRpClkSrcNumber[9]" = "4" register "PcieRpClkSrcNumber[9]" = "4"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -91,6 +88,8 @@ chip soc/intel/skylake
device domain 0 on device domain 0 on
device ref south_xhci on device ref south_xhci on
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */
[1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */

5
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@@ -93,9 +93,6 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[8]" = "6"
register "PcieRpClkReqNumber[16]" = "7" register "PcieRpClkReqNumber[16]" = "7"
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -118,6 +115,8 @@ chip soc/intel/skylake
device domain 0 on device domain 0 on
device ref south_xhci on device ref south_xhci on
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MAX(OC2), /* Type-C Port */ [0] = USB2_PORT_MAX(OC2), /* Type-C Port */
[1] = USB2_PORT_MAX(OC5), /* Front panel */ [1] = USB2_PORT_MAX(OC5), /* Front panel */

6
src/mainboard/intel/saddlebrook/devicetree.cb
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@@ -120,10 +120,6 @@ chip soc/intel/skylake
register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[5]" = "0"
register "PcieRpClkReqNumber[12]" = "1" register "PcieRpClkReqNumber[12]" = "1"
# USB related
register "SsicPortEnable" = "1"
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI # Must leave UART0 enabled or SD/eMMC will not work as PCI
@@ -156,6 +152,8 @@ chip soc/intel/skylake
device domain 0 on device domain 0 on
device ref igpu on end device ref igpu on end
device ref south_xhci on device ref south_xhci on
register "SsicPortEnable" = "1"
register "usb2_ports" = "{ register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */
[1] = USB2_PORT_MID(OC3), /* Touch Pad */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */