Merge branch 'master' into system76

.editorconfig

@@ -0,0 +1,11 @@
+# EditorConfig: https://EditorConfig.org
+
+root = true
+
+[*]
+indent_style = tab
+tab_width = 8
+charset = utf-8
+insert_final_newline = true
+end_of_line = lf
+trim_trailing_whitespace = true

.gitmodules

@@ -34,3 +34,6 @@
 	url = https://github.com/coreboot/intel-microcode.git
 	update = none
 	ignore = dirty
+[submodule "3rdparty/ffs"]
+	path = 3rdparty/ffs
+	url = https://github.com/coreboot/ffs.git

AUTHORS

@@ -2,13 +2,100 @@
 #
 # This does not necessarily list everyone who has contributed code, since in
 # some cases, their employer may be the copyright holder.  To see the full list
-# of contributors, see the revision history in source control.
+# of contributors, and their email addresses, see the revision history in source
-# git log --pretty=format:%an | sort | uniq
+# control.
-#
+# Run the below commands in the coreboot repo for additional information.
+# To see a list of contributors: git log --pretty=format:%an | sort | uniq
+# For patches adding or removing a name: git log -i -S "NAME" --source --all
 
+9elements Agency GmbH
+Advanced Micro Devices, Inc.
+Alex Züpke
 Alexander Couzens
+Alexandru Gagniuc
+Andy Fleming
+ARM Limited and Contributors
+Arthur Heymans
+Carl-Daniel Hailfinger
+coresystems GmbH
+Damien Zammit
+David Hendricks
+David Mosberger-Tang
+Denis Dowling
+DENX Software Engineering
+DMP Electronics Inc.
+Drew Eckhardt
+Egbert Eich
+Eric Biederman
+Eswar Nallusamy
+Facebook, Inc.
+Felix Held
+Frederic Potter
+Free Software Foundation, Inc.
+Freescale Semiconductor, Inc.
+Gary Jennejohn
+Gerd Hoffmann
+Google LLC
+Greg Watson
+Imagination Technologies
+Intel Corporation
+Jason Zhao
+Jordan Crouse
+Joseph Smith
+Keith Hui
+Kshitij
+Kyösti Mälkki
+Lei Wen
+Li-Ta Lo
+Libra Li
+Linus Torvalds
+Linux Networx, Inc.
+Marc Jones
+Marek Vasut
+Marius Gröger
+Martin Mares
+Marvell Semiconductor Inc.
+MediaTek Inc.
+MontaVista Software, Inc.
+Myles Watson
+Nicholas Sielicki
+Nick Barker
+Nico Huber
+Patrick Georgi
+Patrick Rudolph
+PC Engines GmbH
+Per Odlund
+Peter Stuge
+Raptor Engineering, LLC
+Richard Woodruff
+Ronald G. Minnich
+Rudolf Marek
+Russell King
+Sage Electronic Engineering, LLC
+SciTech Software, Inc.
+secunet Security Networks AG
+Siemens AG
+Silicon Integrated System Corporation
+Stefan Reinauer
+Steve Magnani
+SUSE LINUX AG
+Sven Schnelle
+Syed Mohammed Khasim
+Texas Instruments
+The Linux Foundation
+Timothy Pearson
+Tyan Computer Corp.
+Uwe Hermann
+VIA Technologies, Inc
+Wolfgang Denk
+Yinghai Lu
 
 
 
 # Directories transferred
 src/acpi
+src/arch
+src/commonlib
+src/console
+src/cpu
+src/device

Documentation/acpi/devicetree.md

@@ -0,0 +1,234 @@
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI busses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+## Device drivers
+
+Let's take a look at an example entry from
+``src/mainboard/google/hatch/variant/hatch/overridetree.cb``:
+
+```
+device pci 15.0 on
+	chip drivers/i2c/generic
+		register "hid" = ""ELAN0000""
+		register "desc" = ""ELAN Touchpad""
+		register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+		register "wake" = "GPE0_DW0_21"
+		device i2c 15 on end
+	end
+end # I2C #0
+```
+
+When this entry is processed during ramstage, it will create a device in the
+ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
+generation routines in coreboot actually generate the raw bytecode that
+represents the device's structure, but looking at ASL code is easier to
+understand; see below for what the disassembled bytecode looks like:
+
+```
+Scope (\_SB.PCI0.I2C0)
+{
+    Device (D015)
+    {
+        Name (_HID, "ELAN0000")  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            Return (0x0F)
+        }
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                0x00, ResourceConsumer, , Exclusive, )
+            Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+            {
+                0x0000002D,
+            }
+        })
+        Name (_S0W, 0x04)  // _S0W: S0 Device Wake State
+        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+        {
+            0x15, // GPE #21
+            0x03  // Sleep state S3
+        })
+    }
+}
+```
+
+You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
+names/methods in the Device's scope.
+
+## Utilizing a device driver
+
+The device driver must be enabled for your build.  There will be a CONFIG option
+in the Kconfig file in the directory that the driver is in (e.g.,
+``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
+CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
+mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
+to be compiled into your build.
+
+## Diving into the above example:
+
+Let's take a look at how the devicetree language corresponds to the generated
+ASL.
+
+First, note this:
+
+```
+    chip drivers/i2c/generic
+```
+
+This means that the device driver we're using has a corresponding structure,
+located at ``src/drivers/i2c/generic/chip.h``, named **struct
+drivers_i2c_generic_config** and it contains many properties you can specify to
+be included in the ACPI table.
+
+### hid
+
+```
+    register "hid" = ""ELAN0000""
+```
+
+This corresponds to **const char *hid** in the struct.  In the ACPI ASL, it
+translates to:
+
+```
+    Name (_HID, "ELAN0000") // _HID: Hardware ID
+```
+
+under the device.  **This property is used to match the device to its driver
+during enumeration in the OS.**
+
+### desc
+
+```
+    register "desc" = ""ELAN Touchpad""
+```
+
+corresponds to **const char *desc** and in ASL:
+
+```
+    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
+```
+
+### irq
+
+It also adds the interrupt,
+
+```
+    Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+    {
+        0x0000002D,
+    }
+```
+
+which comes from:
+
+```
+    register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+```
+
+The GPIO pin IRQ settings control the "Edge", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered
+interrupt as opposed to level-triggered; active low means the interrupt is
+triggered on a falling edge).
+
+Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO
+will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
+source.  Also note that the IRQ names are SoC-specific, and you will need to
+find the names in your SoC's header file.  The ACPI_* macros are defined in
+``src/arch/x86/include/arch/acpi_device.h``.
+
+Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
+This is often done in a mainboard-specific file named ``gpio.c``.
+
+### wake
+
+The last register is:
+
+```
+    register "wake" = "GPE0_DW0_21"
+```
+
+which indicates that the method of waking the system using the touchpad will be
+through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
+this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
+elsewhere in the devicetree.
+
+The last bit of the definition of that device includes:
+
+```
+    device i2c 15 on end
+```
+
+which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
+meaning it will be exposed in the ACPI table.  The PCI device that the
+controller is located in determines which I2C bus the device is expected to be
+found on.  In this example, this is I2C bus 0.  This also determines the ACPI
+"Scope" that the device names and methods will live under, in this case
+"\_SB.PCI0.I2C0".
+
+## Other auto-generated names
+
+(see [ACPI specification
+6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
+for more details on ACPI methods)
+
+### _S0W (S0 Device Wake State)
+_S0W indicates the deepest S0 sleep state this device can wake itself from,
+which in this case is 4, representing _D3cold_.
+
+### _PRW (Power Resources for Wake)
+_PRW indicates the power resources and events required for wake.  There are no
+dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
+as well as the deepest sleep state supporting waking the system (3), which is
+S3.
+
+### _STA (Status)
+The _STA method is generated automatically, and its values, 0xF, indicates the
+following:
+
+    Bit [0] – Set if the device is present.
+    Bit [1] – Set if the device is enabled and decoding its resources.
+    Bit [2] – Set if the device should be shown in the UI.
+    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
+
+### _CRS (Current resource settings)
+The _CRS method is generated automatically, as the driver knows it is an I2C
+controller, and so specifies how to configure the controller for proper
+operation with the touchpad.
+
+```
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                    0x00, ResourceConsumer, , Exclusive, )
+```
+
+## Notes
+
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/coding_style.md

@@ -80,11 +80,11 @@ Get a decent editor and don't leave whitespace at the end of lines.
 Coding style is all about readability and maintainability using commonly
 available tools.
 
-The limit on the length of lines is 80 columns and this is a strongly
+The limit on the length of lines is 96 columns and this is a strongly
 preferred limit.
 
-Statements longer than 80 columns will be broken into sensible chunks,
+Statements longer than 96 columns will be broken into sensible chunks,
-unless exceeding 80 columns significantly increases readability and does
+unless exceeding 96 columns significantly increases readability and does
 not hide information. Descendants are always substantially shorter than
 the parent and are placed substantially to the right. The same applies
 to function headers with a long argument list. However, never break

Documentation/getting_started/gerrit_guidelines.md

@@ -46,11 +46,11 @@ clarification, see the Developer's Certificate of Origin in the coreboot
 * Let non-trivial patches sit in a review state for at least 24 hours
 before submission. Remember that there are coreboot developers in timezones
 all over the world, and everyone should have a chance to contribute.
-Trivial patches would be things like whitespace changes or spelling fixes.
+Trivial patches would be things like whitespace changes or spelling fixes,
-In general, small changes that don’t impact the final binary output. The
+in general those that don’t impact the final binary output. The
 24-hour period would start at submission, and would be restarted at any
 update which significantly changes any part of the patch. Patches can be
-'Fast-tracked' and submitted in under this 24 hour with the agreement of at
+'Fast-tracked' and submitted in under 24 hours with the agreement of at
 least 3 +2 votes.
 
 * Do not +2 patches that you authored or own, even for something as trivial

Documentation/getting_started/kconfig.md

@@ -73,9 +73,6 @@ These variables are typically set in the makefiles or on the make command line.
 These variables were added to Kconfig specifically for coreboot and are not
 included in the Linux version.
 
-- COREBOOT_BUILD_DIR=path for temporary files.   This is used by coreboot’s
-  abuild tool.
-
 - KCONFIG_STRICT=value. Define to enable warnings as errors.   This is enabled
   in coreboot, and should not be changed.
 

Documentation/index.md

@@ -161,7 +161,7 @@ for example OpenBSD, is probably the closest cousin of our approach.
 Contents:
 
 * [Getting Started](getting_started/index.md)
-* [Rookie Guide](lessons/index.md)
+* [Tutorial](tutorial/index.md)
 * [Coding Style](coding_style.md)
 * [Project Ideas](contributing/project_ideas.md)
 * [Code of Conduct](community/code_of_conduct.md)
@@ -172,6 +172,7 @@ Contents:
 * [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
+* [Adding devices to a device tree](acpi/devicetree.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
 * [Display panel-specific documentation](gfx/display-panel.md)
 * [Architecture-specific documentation](arch/index.md)

Documentation/lessons/index.md

@@ -1,4 +0,0 @@
-# Rookie Guide
-
-* [Lesson 1: Starting from scratch](lesson1.md)
-* [Lesson 2: Submitting a patch to coreboot.org](lesson2.md)

Documentation/mainboard/emulation/qemu-aarch64.md

@@ -7,7 +7,7 @@ as a payload for QEMU/AArch64.
 ```bash
 qemu-system-aarch64 -bios ./build/coreboot.rom \
     -M virt,secure=on,virtualization=on -cpu cortex-a53 \
-    -nographic -m 8912M
+    -nographic -m 8192M
 ```
 
 - The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit
@@ -17,6 +17,7 @@ have the right to access EL3/EL2 registers. You need to enable EL3/EL2
 via `-machine secure=on,virtualization=on`.
 - You need to specify the size of memory more than 544 MiB because 512
 MiB is reserved for the kernel.
+- The maximum size of memory is 255GiB (-m 261120).
 
 ## Building coreboot with an arbitrary FIT payload
 There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select
@@ -30,7 +31,7 @@ You can get the DTB from QEMU with the following command.
 ```
 $ qemu-system-aarch64 \
     -M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \
-    -cpu cortex-a53 -nographic -m 2048M
+    -cpu cortex-a53 -nographic -m 8192M
 ```
 
 ### 2. Build a FIT image with a DTB

Documentation/mainboard/index.md

@@ -2,6 +2,11 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## ASRock
+
+- [H81M-HDS](asrock/h81m-hds.md)
+- [H110M-DVS](asrock/h110m-dvs.md)
+
 ## ASUS
 
 - [F2A85-M](asus/f2a85-m.md)
@@ -9,11 +14,6 @@ This section contains documentation about coreboot on specific mainboards.
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 
-## ASRock
-
-- [H81M-HDS](asrock/h81m-hds.md)
-- [H110M-DVS](asrock/h110m-dvs.md)
-
 ## Cavium
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
@@ -26,12 +26,6 @@ The boards in this section are not real mainboards, but emulators.
 - [Qemu RISC-V emulator](emulation/qemu-riscv.md)
 - [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
 
-## Intel
-
-- [DG43GT](intel/dg43gt.md)
-- [IceLake RVP](intel/icelake_rvp.md)
-- [KBLRVP11](intel/kblrvp11.md)
-
 ## Facebook
 
 - [FBG-1701](facebook/fbg1701.md)
@@ -48,11 +42,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Dragonegg](google/dragonegg.md)
 
-## Open Cellular
-
-- [Elgon](opencellular/elgon.md)
-- [Rotundu](opencellular/rotundu.md)
-
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
@@ -63,6 +52,12 @@ The boards in this section are not real mainboards, but emulators.
 - [EliteBook common](hp/elitebook_series.md)
 - [EliteBook 8760w](hp/8760w.md)
 
+## Intel
+
+- [DG43GT](intel/dg43gt.md)
+- [IceLake RVP](intel/icelake_rvp.md)
+- [KBLRVP11](intel/kblrvp11.md)
+
 ## Lenovo
 
 - [Mainboard codenames](lenovo/codenames.md)
@@ -70,10 +65,6 @@ The boards in this section are not real mainboards, but emulators.
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
-## Portwell
-
-- [PQ7-M107](portwell/pq7-m107.md)
-
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)
@@ -92,17 +83,23 @@ The boards in this section are not real mainboards, but emulators.
 
 - [MS-7707](msi/ms7707/ms7707.md)
 
-## PC Engines
+## Open Cellular
 
-- [APU2](pcengines/apu2.md)
+- [Elgon](opencellular/elgon.md)
-
+- [Rotundu](opencellular/rotundu.md)
-## Roda
-
-- [RK9 Flash Header](roda/rk9/flash_header.md)
 
 ## PC Engines
 
 - [APU1](pcengines/apu1.md)
+- [APU2](pcengines/apu2.md)
+
+## Portwell
+
+- [PQ7-M107](portwell/pq7-m107.md)
+
+## Roda
+
+- [RK9 Flash Header](roda/rk9/flash_header.md)
 
 ## SiFive
 
@@ -111,6 +108,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Supermicro
 
 - [X10SLM+-F](supermicro/x10slm-f.md)
+- [X11 LGA1151 series](supermicro/x11-lga1151-series/index.md)
 
 ## UP
 

Documentation/mainboard/supermicro/x10slm-f.md

@@ -12,7 +12,7 @@ Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
 
 ```eval_rst
 If you haven't already, build the coreboot toolchain as described in
-:doc:`../../lessons/lesson1`.
+:doc:`../../tutorial/part1`.
 ```
 
 A fully working image should be possible so long as you have the
@@ -135,7 +135,7 @@ for caveats.
   can't be used for temperature readings.
 
 - There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
+  the Super I/O hardware monitor can only obtain valid CPU temperature
   readings from the PECI agent, but the required driver doesn't exist
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS, and hence the OS can do fan control.

Documentation/mainboard/supermicro/x11-lga1151-series/index.md

@@ -0,0 +1,7 @@
+# X11 LGA1151 series
+
+The supermicros X11 series with socket LGA1151 are mostly the same boards with some minor
+differences in internal and external interfaces like available PCIe slots, 1 GbE, 10 GbE,
+IPMI etc. This is why those boards are grouped as "X11 LGA1151 series".
+
+- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md

@@ -0,0 +1,73 @@
+# Supermicro X11SSH-TF
+
+This section details how to run coreboot on the [Supermicro X11SSH-TF].
+
+## Required proprietary blobs
+
+* [Intel FSP2.0]
+* Intel ME
+
+## Flashing coreboot
+
+The board can be flashed externally using *some* programmers.
+The CH341 was found working, while Dediprog won't detect the chip.
+
+For more details have a look at the [flashing tutorial].
+
+The flash IC can be found between the two PCIe slots near the southbridge:
+![](x11ssh-tf_flash.jpg)
+
+## BMC (IPMI)
+
+This board has an ASPEED [AST2400], which has BMC functionality. The
+BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the
+mainboard near the [AST2400]. This chip is an [MX25L25635F].
+
+## Known issues
+
+- Intel SGX causes secondary APs to crash (disabled for now).
+- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
+- SMBus / I2C does not work (interrupt timeout)
+
+## Tested and working
+
+- USB ports
+- M.2 2280 NVMe slot
+- 2x 10GB Ethernet
+- SATA
+- RS232
+- VGA on Aspeed
+- Super I/O initialisation
+- ECC DRAM detection
+- PCIe slots
+- TPM on TPM expansion header
+- BMC (IPMI)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Kaby Lake                                  |
++------------------+--------------------------------------------------+
+| PCH              | Intel C236                                       |
++------------------+--------------------------------------------------+
+| Super I/O        | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+| Coprocessor      | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+- [Board manual]
+
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
+[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
+[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
+[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
+[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF

Documentation/security/intel/txt.md

@@ -90,11 +90,11 @@ correct state. If it's not the SINIT ACM will reset the platform.
 
 ## For developers
 ### Configuring Intel TXT in Kconfig
-Enable ``TEE_INTEL_TXT`` and set the following:
+Enable ``INTEL_TXT`` and set the following:
 
-``TEE_INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel
+``INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel
 
-``TEE_INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel
+``INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel
 ### Print TXT status as early as possible
 Add platform code to print the TXT status as early as possible, as the register
 is cleared on cold reset.

Documentation/soc/intel/fsp/index.md

@@ -45,6 +45,8 @@ those are fixed. If possible a workaround is described here as well.
 
 * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf)
 
+* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786)
+
 ## Additional Features in FSP 2.1 specification
 
 - [PPI](ppi/ppi.md)

Documentation/superio/common/ssdt.md

@@ -0,0 +1,56 @@
+# SuperIO SSTD generator
+
+This page describes the common SSDT ACPI generator for SuperIO chips that can
+be found in coreboot.
+
+## Functional description
+
+In order to automatically generate ACPI functions you need to add
+a new `chip superio/common` and `device pnp xx.0 on` to your devicetree.
+
+The xx denotes the hexadecimal address of the SuperIO.
+
+Place the regular LDN pnp devices behind those two entries.
+
+The code will automatically guess the function based on the decoded
+I/O range and ISA IRQ number.
+
+## Example devicetree.cb
+
+This example is based on AST2400.
+
+```code
+# Add a "container" for proper ACPI code generation
+chip superio/common
+  device pnp 2e.0 on # just for the base device, not for the LDNs
+    chip superio/aspeed/ast2400
+      device pnp 2e.0 off  end
+      device pnp 2e.2 on # SUART1
+        io 0x60 = 0x3f8
+        irq 0x70 = 4
+      end
+      device pnp 2e.3 on # SUART2
+        io 0x60 = 0x2f8
+        irq 0x70 = 3
+      end
+      device pnp 2e.4 on # SWC
+        io 0x60 = 0xa00
+        io 0x62 = 0xa10
+        io 0x64 = 0xa20
+        io 0x66 = 0xa30
+        irq 0x70 = 0
+      end
+    end
+  end
+end
+```
+
+## TODO
+
+1) Add ACPI HIDs to every SuperIO driver
+2) Don't guess ACPI HID of LDNs if it's known
+3) Add "enter config" and "exit config" bytes
+4) Generate support methods that allow
+   * Setting resource settings at runtime
+   * Getting resource settings at runtime
+   * Disabling LDNs at runtime

Documentation/superio/index.md

@@ -5,3 +5,6 @@ This section contains documentation about coreboot on specific SuperIOs.
 ## Nuvoton
 
 - [NPCD378](nuvoton/npcd378.md)
+
+## Common
+- [SSDT generator for generic SuperIOs](common/ssdt.md)

Documentation/tutorial/index.md

@@ -0,0 +1,4 @@
+# Tutorial
+
+* [Part 1: Starting from scratch](part1.md)
+* [Part 2: Submitting a patch to coreboot.org](part2.md)

Documentation/tutorial/part1.md

@@ -1,5 +1,5 @@
-coreboot Lesson 1: Starting from scratch
+Tutorial, part 1: Starting from scratch
-========================================
+===========================================
 
 From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
 a very basic build:

Documentation/tutorial/part2.md

@@ -1,4 +1,4 @@
-# coreboot Lesson 2: Submitting a patch to coreboot.org
+# Tutorial, part 2: Submitting a patch to coreboot.org
 
 ## Part 1: Setting up an account at coreboot.org
 

Documentation/vendorcode/index.md

@@ -5,3 +5,4 @@ This section contains documentation about coreboot on specific vendorcode.
 ## Vendor
 
 - [Cavium](cavium/index.md)
+- [Eltan](eltan/index.md)

Makefile

@@ -30,6 +30,9 @@
 ## SUCH DAMAGE.
 ##
 
+ifneq ($(words $(CURDIR)),1)
+    $(error Error: Path to the main directory cannot contain spaces)
+endif
 top := $(CURDIR)
 src := src
 srck := $(top)/util/kconfig
@@ -42,6 +45,12 @@ absobj := $(abspath $(obj))
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
 COREBOOT_EXPORTS += top src srck obj objutil objk
 
+# reproducible builds
+LANG:=C
+LC_ALL:=C
+TZ:=UTC0
+COREBOOT_EXPORTS += LANG LC_ALL TZ
+
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
 KCONFIG_AUTOADS := $(obj)/cb-config.ads
@@ -129,6 +138,12 @@ NOMKDIR:=1
 endif
 endif
 
+.xcompile: util/xcompile/xcompile
+	rm -f $@
+	$< $(XGCCPATH) > $@.tmp
+	\mv -f $@.tmp $@ 2> /dev/null
+	rm -f $@.tmp
+
 -include $(TOPLEVEL)/site-local/Makefile.inc
 
 ifeq ($(NOCOMPILE),1)
@@ -148,12 +163,6 @@ include $(DOTCONFIG)
 # to silence stupid warnings about a file that would be generated anyway.
 $(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile)))
 
-.xcompile: util/xcompile/xcompile
-	rm -f $@
-	$< $(XGCCPATH) > $@.tmp
-	\mv -f $@.tmp $@ 2> /dev/null
-	rm -f $@.tmp
-
 -include .xcompile
 
 ifneq ($(XCOMPILE_COMPLETE),1)

Makefile.inc

@@ -402,7 +402,7 @@ endif
 CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
-CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits
+CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
@@ -497,14 +497,14 @@ build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION
 # Report new `build.ht` as dependency if `build.h` differs.
 build_h_check := \
 	export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \
-	util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \
+	util/genbuild_h/genbuild_h.sh .xcompile >$(build_h)t 2>/dev/null; \
 	cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t
 
 $(build_h): $$(shell $$(build_h_check))
 	@printf "    GEN        build.h\n"
 	mv $< $@
 
-build-dirs:
+build-dirs $(objcbfs) $(objgenerated):
 	mkdir -p $(objcbfs) $(objgenerated)
 
 #######################################################################
@@ -646,7 +646,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL)
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL)
 
 ###########################################################################
 # Common recipes for all stages
@@ -706,7 +706,7 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.raw.elf
 	$(OBJCOPY_bootblock) -O binary $< $@
 
 ifneq ($(CONFIG_HAVE_BOOTBLOCK),y)
-$(objcbfs)/bootblock.bin:
+$(objcbfs)/bootblock.bin: $(objcbfs)
 	dd if=/dev/zero of=$@ bs=64 count=1
 endif
 

configs/config.intel_galileo_gen2.debug

@@ -3,7 +3,6 @@ CONFIG_VENDOR_INTEL=y
 CONFIG_BOARD_INTEL_GALILEO=y
 # CONFIG_FSP_DEBUG_ALL is not set
 CONFIG_DISPLAY_MTRRS=y
-CONFIG_DISPLAY_SMM_MEMORY_MAP=y
 CONFIG_DISPLAY_ESRAM_LAYOUT=y
 CONFIG_BOOTBLOCK_NORMAL=y
 CONFIG_ON_DEVICE_ROM_LOAD=y

payloads/coreinfo/Makefile

@@ -83,7 +83,7 @@ OBJCOPY := $(OBJCOPY_$(ARCH-y))
 LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc
 LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas
 
-CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror
+CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
 CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES)
 
 ifneq ($(strip $(HAVE_DOTCONFIG)),)

payloads/external/LinuxBoot/targets/linux.mk

@@ -29,11 +29,13 @@ tarball_dir:=$(project_dir)/tarball
 decompress_flag=.done
 
 OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy
+KERNEL_MAKE_FLAGS = \
+	ARCH=$(ARCH-y)
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y)
 	kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION)
 else
-	kernel_version:=$(shell curl -s -k https://www.kernel.org/feeds/kdist.xml | \
+	kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \
 		sed -n -e 's@.*<guid isPermaLink="false">\(.*\)</guid>.*@\1@p' | \
 		awk -F ',' '/$(TAG-y)/{ print $$3 }' | \
 		head -n 1)
@@ -67,7 +69,7 @@ ifneq ($(shell [[ -d "$(kernel_dir)" && -f "$(kernel_dir)/$(decompress_flag)" ]]
 	if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \
 	echo "    WWW        $(kernel_tarball).xz"; \
 	cd $(tarball_dir); \
-	curl -OLs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \
+	curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \
 	cd $(pwd); \
 	fi
 endif
@@ -90,15 +92,15 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG),y)
 else
 	cp $(ARCH-y)/defconfig $(kernel_dir)/.config
 endif
-	$(MAKE) -C $(kernel_dir) olddefconfig ARCH=$(ARCH-y)
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig
 
 build: $(kernel_dir)/.config
 	@echo "    MAKE       Linux $(kernel_version)"
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y)
-	$(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) bzImage
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage
 else
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y)
-	$(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) vmlinux
+	$(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux
 endif
 endif
 

payloads/external/Makefile.inc

@@ -29,6 +29,11 @@ endif
 ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y)
 PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config
 $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf
+ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),)
+  BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
+else
+  BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))))
+endif
 #TODO: Figure out version
 endif
 
@@ -114,7 +119,7 @@ endif
 
 payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL)
 	$(MAKE) -C payloads/external/depthcharge \
-		BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \
+		BOARD=$(BOARD) \
 		MFLAGS= MAKEFLAGS= \
 		DEPTHCHARGE_MASTER=$(CONFIG_DEPTHCHARGE_MASTER) \
 		DEPTHCHARGE_STABLE=$(CONFIG_DEPTHCHARGE_STABLE) \
@@ -128,14 +133,14 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 	$(MAKE) -C payloads/external/tianocore all \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
-		CONFIG_TIANOCORE_MASTER=$(CONFIG_TIANOCORE_MASTER) \
-		CONFIG_TIANOCORE_STABLE=$(CONFIG_TIANOCORE_STABLE) \
-		CONFIG_TIANOCORE_REVISION=$(CONFIG_TIANOCORE_REVISION) \
 		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
 		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
 		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
 		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
+		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \

payloads/external/depthcharge/Kconfig

@@ -35,6 +35,11 @@ config PAYLOAD_FILE
 	string
 	default "payloads/external/depthcharge/depthcharge/build/depthcharge.elf"
 
+config MAINBOARD_DEPTHCHARGE
+	string ""
+	help
+	   Override BOARD setting for depthcharge
+
 config LP_DEFCONFIG_OVERRIDE
 	bool "Use default libpayload config"
 	help

payloads/external/tianocore/Kconfig

@@ -7,38 +7,32 @@ config PAYLOAD_FILE
 	  The result of a corebootPkg build
 
 choice
-	prompt "Tianocore version"
+	prompt "Tianocore payload"
-	default TIANOCORE_STABLE
+	default TIANOCORE_COREBOOTPAYLOAD
 	help
-	  Select which version of Tianocore to build (default is to build stable)
+	  Select which type of payload Tianocore will build (default is CorebootPayload)
-	  stable: MrChromebox's customized version of Tianocore which works on most
+	  CorebootPayload: MrChromebox's customized version of Tianocore which works on most
 	  (all?) x86_64 devices
-	  revision: use specific commit or branch to build Tianocore (specified by user)
+	  UEFIPayload: Use upstream Tianocore payload from https://github.com/tianocore/edk2
 
-config TIANOCORE_STABLE
+config TIANOCORE_COREBOOTPAYLOAD
-	bool "stable"
+	bool "CorebootPayload"
 	help
 	  Select this option to build using MrChromebox's custom Tianocore tree
 	  i.e. a version of Tianocore that builds without any errors and just works.
 
-config TIANOCORE_REVISION
+config TIANOCORE_UEFIPAYLOAD
-	bool "git revision"
+	bool "UEFIPayload"
 	help
-	  Select this option if you have a specific commit or branch
+	  Select this option if you want to use upstream EDK2 to build Tianocore.
-	  that you want to use from either MrChromebox's tree or upstream
-	  EDK2 from which to build Tianocore.
-
-	  You will be able to specify the name of a branch or a commit id
-	  later.
 
 endchoice
 
 config TIANOCORE_REVISION_ID
 	string "Insert a commit's SHA-1 or a branch name"
-	depends on TIANOCORE_REVISION
-	default "upstream/master"
 	help
-	   The commit's SHA-1 or branch name of the revision to use.
+	   The commit's SHA-1 or branch name of the revision to use. Choose "upstream/master"
+	   for master branch of Tianocore release on github.
 
 choice
 	prompt "Target architecture"
@@ -89,7 +83,7 @@ config TIANOCORE_USE_8254_TIMER
 
 config TIANOCORE_BOOTSPLASH_IMAGE
 	bool "Use a custom bootsplash image"
-	depends on TIANOCORE_STABLE
+	depends on TIANOCORE_COREBOOTPAYLOAD
 	help
 	  Select this option if you have a bootsplash image that you would
 	  like to be used. If this option is not selected, the default
@@ -98,6 +92,7 @@ config TIANOCORE_BOOTSPLASH_IMAGE
 config TIANOCORE_BOOTSPLASH_FILE
 	string "Tianocore Bootsplash path and filename"
 	depends on TIANOCORE_BOOTSPLASH_IMAGE
+	depends on TIANOCORE_COREBOOTPAYLOAD
 	default "bootsplash.bmp"
 	help
 	  The path and filename of the file to use as graphical bootsplash

payloads/external/tianocore/Kconfig.name

@@ -1,5 +1,5 @@
 config PAYLOAD_TIANOCORE
-	bool "Tianocore coreboot payload package"
+	bool "Tianocore payload"
 	depends on ARCH_X86
 	help
 	  Select this option if you want to build a coreboot image

payloads/external/tianocore/Makefile

@@ -22,9 +22,19 @@ project_git_repo=https://github.com/mrchromebox/edk2
 project_git_branch=coreboot_fb
 upstream_git_repo=https://github.com/tianocore/edk2
 
+ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
+bootloader=UefiPayloadPkg
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS)
+TAG=upstream/master
+else
+bootloader=CorebootPayloadPkg
 # STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
-TAG-$(CONFIG_TIANOCORE_STABLE)=origin/$(project_git_branch)
+TAG=origin/$(project_git_branch)
-TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID)
+endif
+
+ifneq ($(CONFIG_TIANOCORE_REVISION_ID),)
+TAG=$(CONFIG_TIANOCORE_REVISION_ID)
+endif
 
 export EDK_TOOLS_PATH=$(project_dir)/BaseTools
 
@@ -39,9 +49,9 @@ TIMER=-DUSE_HPET_TIMER
 endif
 
 ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-	BUILD_STR=-a IA32 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -b $(BUILD_TYPE) $(TIMER)
+	BUILD_STR=-a IA32 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 else
-	BUILD_STR=-a IA32 -a X64 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b $(BUILD_TYPE) $(TIMER)
+	BUILD_STR=-a IA32 -a X64 -t COREBOOT -p $(bootloader)/$(bootloader)Ia32X64.dsc -b $(BUILD_TYPE) $(TIMER) $(build_flavor)
 endif
 
 all: clean build
@@ -56,13 +66,13 @@ update: $(project_dir)
 	cd  $(project_dir); \
 		echo "    Fetching new commits from the $(project_name) repo"; \
 		git fetch --multiple origin upstream 2>/dev/null; \
-		if ! git rev-parse --verify -q $(TAG-y) >/dev/null; then \
+		if ! git rev-parse --verify -q $(TAG) >/dev/null; then \
-			echo "    $(TAG-y) is not a valid git reference"; \
+			echo "    $(TAG) is not a valid git reference"; \
 			exit 1; \
 		fi; \
 		if git describe --all --dirty | grep -qv dirty; then \
-			echo "    Checking out $(project_name) revision $(TAG-y)"; \
+			echo "    Checking out $(project_name) revision $(TAG)"; \
-			git checkout --detach $(TAG-y); \
+			git checkout --detach $(TAG); \
 		else \
 			echo "    Working directory not clean; will not overwrite"; \
 		fi
@@ -80,7 +90,7 @@ checktools:
 
 build: update checktools
 	unset CC; $(MAKE) -C $(project_dir)/BaseTools
-	echo " build $(project_name) $(TAG-y)"
+	echo " build $(project_name) $(TAG)"
 	if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \
 		echo "    Copying custom bootsplash image"; \
 		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
@@ -99,7 +109,7 @@ build: update checktools
 			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
 		fi; \
 		build $(BUILD_STR); \
-		mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
+		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
 		git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true
 
 clean:

payloads/libpayload/Makefile.inc

@@ -62,7 +62,7 @@ INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h
 CFLAGS +=  $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3
 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
 CFLAGS += -ffunction-sections -fdata-sections
-CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
+CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla
 CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS += -Wstrict-aliasing -Wshadow -Werror
 

payloads/libpayload/drivers/usb/usb.c

@@ -265,6 +265,8 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0)
 		}
 		return bMaxPacketSize0;
 	case SUPER_SPEED:
+	/* Intentional fallthrough */
+	case SUPER_SPEED_PLUS:
 		if (bMaxPacketSize0 != 9) {
 			usb_debug("Invalid MPS0: 0x%02x\n", bMaxPacketSize0);
 			bMaxPacketSize0 = 9;
@@ -284,6 +286,8 @@ int speed_to_default_mps(usb_speed speed)
 	case HIGH_SPEED:
 		return 64;
 	case SUPER_SPEED:
+	/* Intentional fallthrough */
+	case SUPER_SPEED_PLUS:
 	default:
 		return 512;
 	}
@@ -319,6 +323,8 @@ usb_decode_interval(usb_speed speed, const endpoint_type type, const unsigned ch
 			return LOG2(bInterval);
 		}
 	case SUPER_SPEED:
+	/* Intentional fallthrough */
+	case SUPER_SPEED_PLUS:
 		switch (type) {
 		case ISOCHRONOUS: case INTERRUPT:
 			return bInterval - 1;
@@ -657,7 +663,7 @@ usb_detach_device(hci_t *controller, int devno)
 int
 usb_attach_device(hci_t *controller, int hubaddress, int port, usb_speed speed)
 {
-	static const char* speeds[] = { "full", "low", "high", "super" };
+	static const char *speeds[] = { "full", "low", "high", "super", "ultra" };
 	usb_debug ("%sspeed device\n", (speed < sizeof(speeds) / sizeof(char*))
 		? speeds[speed] : "invalid value - no");
 	int newdev = set_address (controller, speed, port, hubaddress);
@@ -692,6 +698,14 @@ usb_generic_init (usbdev_t *dev)
 	}
 }
 
+/*
+ * returns the speed is above SUPER_SPEED or not
+ */
+_Bool is_usb_speed_ss(usb_speed speed)
+{
+	return (speed == SUPER_SPEED || speed == SUPER_SPEED_PLUS);
+}
+
 /*
  * returns the address of the closest USB2.0 hub, which is responsible for
  * split transactions, along with the number of the used downstream port

payloads/libpayload/drivers/usb/usbhub.c

@@ -35,16 +35,40 @@
 /* assume that host_to_device is overwritten if necessary */
 #define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp)
 /* status (and status change) bits */
-#define PORT_CONNECTION 0x1
+#define PORT_CONNECTION		0x01
-#define PORT_ENABLE 0x2
+#define PORT_ENABLE		0x02
+#define PORT_SUSPEND		0x04
+#define PORT_OVER_CURRENT	0x08
 #define PORT_RESET		0x10
+#define BH_PORT_RESET		0x20
+#define PORT_LINK_STATE		0x40
+#define PORT_CONFIG_ERROR	0x80
 /* feature selectors (for setting / clearing features) */
-#define SEL_PORT_RESET 0x4
+#define SEL_PORT_RESET		0x04
-#define SEL_PORT_POWER 0x8
+#define SEL_PORT_POWER		0x08
 #define SEL_C_PORT_CONNECTION	0x10
+#define SEL_C_PORT_ENABLE	0x11
+#define SEL_C_PORT_SUSPEND	0x12
+#define SEL_C_PORT_OVER_CURRENT	0x13
+#define SEL_C_PORT_RESET	0x14
+#define SEL_C_PORT_LINK_STATE	0x19
+#define SEL_C_PORT_CONFIG_ERROR	0x1a
+#define SEL_C_BH_PORT_RESET	0x1d
 /* request type (USB 3.0 hubs only) */
 #define SET_HUB_DEPTH		12
 
+static endpoint_t *
+usb_hub_interrupt_ep(usbdev_t *const dev)
+{
+	int i;
+	for (i = 0; i < dev->num_endp; ++i) {
+		if (dev->endpoints[i].type == INTERRUPT &&
+				dev->endpoints[i].direction == IN)
+			return &dev->endpoints[i];
+	}
+	return NULL;
+}
+
 static int
 usb_hub_port_status_changed(usbdev_t *const dev, const int port)
 {
@@ -96,8 +120,8 @@ usb_hub_port_speed(usbdev_t *const dev, const int port)
 	int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
 	if (ret >= 0 && (buf[0] & PORT_ENABLE)) {
 		/* SuperSpeed hubs can only have SuperSpeed devices. */
-		if (dev->speed == SUPER_SPEED)
+		if (is_usb_speed_ss(dev->speed))
-			return SUPER_SPEED;
+			return dev->speed;
 
 		/*[bit] 10  9  (USB 2.0 port status word)
 		 *      0   0  full speed
@@ -169,14 +193,100 @@ usb_hub_port_initialize(usbdev_t *const dev, const int port)
 		return;
 	if (buf[1] & PORT_CONNECTION)
 		clear_feature(dev, port, SEL_C_PORT_CONNECTION, DR_PORT);
-	if (buf[0] & PORT_CONNECTION)
+	if (buf[0] & PORT_CONNECTION) {
+		usb_debug("usbhub: Port coldplug at %d\n", port);
 		generic_hub_scanport(dev, port);
 	}
+}
+
+static int
+usb_hub_handle_port_change(usbdev_t *const dev, const int port)
+{
+	static const struct {
+		unsigned short change_bit;
+		unsigned short clear_sel;
+	} change_bits[] = {
+		{ PORT_CONNECTION,	SEL_C_PORT_CONNECTION	},
+		{ PORT_ENABLE,		SEL_C_PORT_ENABLE	},
+		{ PORT_SUSPEND,		SEL_C_PORT_SUSPEND	},
+		{ PORT_OVER_CURRENT,	SEL_C_PORT_OVER_CURRENT	},
+		{ PORT_RESET,		SEL_C_PORT_RESET	},
+		{ BH_PORT_RESET,	SEL_C_BH_PORT_RESET	},
+		{ PORT_LINK_STATE,	SEL_C_PORT_LINK_STATE	},
+		{ PORT_CONFIG_ERROR,	SEL_C_PORT_CONFIG_ERROR	},
+	};
+	int ret = 0;
+	unsigned int i;
+	unsigned short checked_bits = 0;
+	unsigned short buf[2] = { 0, 0 };
+
+	ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Second word holds the change bits. The interrupt transfer shows
+	 * a logical or of these bits, so we have to clear them all.
+	 */
+	for (i = 0; i < ARRAY_SIZE(change_bits); ++i) {
+		if (buf[1] & change_bits[i].change_bit)
+			clear_feature(dev, port, change_bits[i].clear_sel, DR_PORT);
+		checked_bits |= change_bits[i].change_bit;
+	}
+	if (buf[1] & ~checked_bits)
+		usb_debug("usbhub: Spurious change bit at port %d\n", port);
+
+	/* Now, handle connection changes. */
+	if (buf[1] & PORT_CONNECTION) {
+		usb_debug("usbhub: Port change at %d\n", port);
+		ret = generic_hub_scanport(dev, port);
+	}
+	return ret;
+}
+
+static void
+usb_hub_poll(usbdev_t *const dev)
+{
+	unsigned int port, i;
+	u8 buf[32] = { 0 };
+	const u8 *ibuf;
+
+	/* First, gather all change bits from finished interrupt transfers. */
+	const size_t port_bytes = MIN(ARRAY_SIZE(buf),
+			div_round_up(GEN_HUB(dev)->num_ports + 1, 8));
+	while ((ibuf = dev->controller->poll_intr_queue(GEN_HUB(dev)->data))) {
+		for (i = 0; i < port_bytes; ++i)
+			buf[i] |= ibuf[i];
+	}
+
+	for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) {
+		/* ports start at bit1; bit0 is hub status change */
+		if (buf[port / 8] & (1 << (port % 8))) {
+			if (usb_hub_handle_port_change(dev, port) < 0)
+				return;
+		}
+	}
+}
+
+static void
+usb_hub_destroy(usbdev_t *const dev)
+{
+	endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev);
+	dev->controller->destroy_intr_queue(intr_ep, GEN_HUB(dev)->data);
+	generic_hub_destroy(dev);
+}
 
 void
 usb_hub_init(usbdev_t *const dev)
 {
-	int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */
+	endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev);
+	if (!intr_ep) {
+		usb_debug("usbhub: ERROR: No interrupt-in endpoint found\n");
+		return;
+	}
+
+	/* Get number of ports from hub decriptor */
+	int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */
 	hub_descriptor_t desc;	/* won't fit the whole thing, we don't care */
 	if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type,
 		dev_recp), type, 0, &desc, sizeof(desc)) != sizeof(desc)) {
@@ -185,12 +295,40 @@ usb_hub_init(usbdev_t *const dev)
 		return;
 	}
 
-	if (dev->speed == SUPER_SPEED)
+	if (is_usb_speed_ss(dev->speed))
 		usb_hub_set_hub_depth(dev);
-	if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops) < 0)
+
+	/*
+	 * Register interrupt transfer:
+	 *   one bit per port + one bit for the hub,
+	 *   20 transfers in the queue, like our HID driver,
+	 *   one transfer per 256ms
+	 */
+	void *const intrq = dev->controller->create_intr_queue(
+			intr_ep, intr_ep->maxpacketsize, 20, 256);
+	if (!intrq) {
+		usb_detach_device(dev->controller, dev->address);
 		return;
+	}
+
+	/*
+	 * Limit the number of ports by the max packet size of
+	 * the interrupt endpoint. This shouldn't be necessary
+	 * but prevents a potential overflow in usb_hub_poll().
+	 */
+	const unsigned int num_ports =
+		MIN(desc.bNbrPorts, intr_ep->maxpacketsize * 8 - 1);
+	if (generic_hub_init(dev, num_ports, &usb_hub_ops)) {
+		dev->controller->destroy_intr_queue(intr_ep, intrq);
+		usb_detach_device(dev->controller, dev->address);
+		return;
+	}
 
 	int port;
-	for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port)
+	for (port = 1; port <= num_ports; ++port)
 		usb_hub_port_initialize(dev, port);
+
+	GEN_HUB(dev)->data = intrq;
+	dev->poll = usb_hub_poll;
+	dev->destroy = usb_hub_destroy;
 }

payloads/libpayload/drivers/usb/usbmsc.c

@@ -157,6 +157,9 @@ reset_transport (usbdev_t *dev)
 	dr.wIndex = 0;
 	dr.wLength = 0;
 
+	if (MSC_INST (dev)->quirks & USB_MSC_QUIRK_NO_RESET)
+		return MSC_COMMAND_FAIL;
+
 	/* if any of these fails, detach device, as we are lost */
 	if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0) < 0 ||
 			clear_stall (MSC_INST (dev)->bulk_in) ||
@@ -185,7 +188,8 @@ initialize_luns (usbdev_t *dev)
 	dr.wValue = 0;
 	dr.wIndex = 0;
 	dr.wLength = 1;
-	if (dev->controller->control (dev, IN, sizeof (dr), &dr,
+	if (MSC_INST (dev)->quirks & USB_MSC_QUIRK_NO_LUNS ||
+	    dev->controller->control (dev, IN, sizeof (dr), &dr,
 			sizeof (msc->num_luns), &msc->num_luns) < 0)
 		msc->num_luns = 0;	/* assume only 1 lun if req fails */
 	msc->num_luns++;	/* Get Max LUN returns number of last LUN */
@@ -218,14 +222,23 @@ wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd,
 static int
 get_csw (endpoint_t *ep, csw_t *csw)
 {
-	if (ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) {
+	hci_t *ctrlr = ep->dev->controller;
+	int ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1);
+
+	/* Some broken sticks send a zero-length packet at the end of their data
+	   transfer which would show up here. Skip it to get the actual CSW. */
+	if (ret == 0)
+		ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1);
+
+	if (ret < 0) {
 		clear_stall (ep);
-		if (ep->dev->controller->bulk
+		if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) {
-				(ep, sizeof (csw_t), (u8 *) csw, 1) < 0) {
 			return reset_transport (ep->dev);
 		}
 	}
-	if (csw->dCSWTag != tag) {
+	if (ret != sizeof(csw_t) || csw->dCSWTag != tag ||
+	    csw->dCSWSignature != csw_signature) {
+		usb_debug ("MSC: received malformed CSW\n");
 		return reset_transport (ep->dev);
 	}
 	return MSC_COMMAND_OK;
@@ -591,14 +604,6 @@ usb_msc_test_unit_ready (usbdev_t *dev)
 void
 usb_msc_init (usbdev_t *dev)
 {
-	int i;
-
-	/* init .data before setting .destroy */
-	dev->data = NULL;
-
-	dev->destroy = usb_msc_destroy;
-	dev->poll = usb_msc_poll;
-
 	configuration_descriptor_t *cd =
 		(configuration_descriptor_t *) dev->configuration;
 	interface_descriptor_t *interface =
@@ -625,6 +630,19 @@ usb_msc_init (usbdev_t *dev)
 		return;
 	}
 
+	usb_msc_force_init (dev, 0);
+}
+
+void usb_msc_force_init (usbdev_t *dev, u32 quirks)
+{
+	int i;
+
+	/* init .data before setting .destroy */
+	dev->data = NULL;
+
+	dev->destroy = usb_msc_destroy;
+	dev->poll = usb_msc_poll;
+
 	dev->data = malloc (sizeof (usbmsc_inst_t));
 	if (!dev->data)
 		fatal("Not enough memory for USB MSC device.\n");
@@ -632,6 +650,7 @@ usb_msc_init (usbdev_t *dev)
 	MSC_INST (dev)->bulk_in = 0;
 	MSC_INST (dev)->bulk_out = 0;
 	MSC_INST (dev)->usbdisk_created = 0;
+	MSC_INST (dev)->quirks = quirks;
 
 	for (i = 1; i <= dev->num_endp; i++) {
 		if (dev->endpoints[i].endpoint == 0)

payloads/libpayload/drivers/usb/xhci_devconf.c

@@ -267,7 +267,7 @@ _free_ic_return:
 static int
 xhci_finish_hub_config(usbdev_t *const dev, inputctx_t *const ic)
 {
-	int type = dev->speed == SUPER_SPEED ? 0x2a : 0x29; /* similar enough */
+	int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */
 	hub_descriptor_t desc;
 
 	if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type,

payloads/libpayload/include/libpayload.h

@@ -445,6 +445,25 @@ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); }
 /** @} */
 
 
+/**
+ * @defgroup mmio MMIO helper functions
+ * @{
+ */
+#if !CONFIG(LP_ARCH_MIPS)
+void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
+			int fifo_stride, int fifo_width);
+void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
+			     void *fifo, int fifo_stride, int fifo_width);
+static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
+				    int fifo_stride, int fifo_width)
+{
+	buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo,
+				fifo_stride, fifo_width);
+}
+#endif
+/** @} */
+
+
 /**
  * @defgroup hash Hashing functions
  * @{

payloads/libpayload/include/usb/usb.h

@@ -210,6 +210,7 @@ typedef enum {
 	LOW_SPEED = 1,
 	HIGH_SPEED = 2,
 	SUPER_SPEED = 3,
+	SUPER_SPEED_PLUS = 4,
 } usb_speed;
 
 struct usbdev {
@@ -293,6 +294,7 @@ int get_descriptor (usbdev_t *dev, int rtype, int descType, int descIdx,
 int set_configuration (usbdev_t *dev);
 int clear_feature (usbdev_t *dev, int endp, int feature, int rtype);
 int clear_stall (endpoint_t *ep);
+_Bool is_usb_speed_ss(usb_speed speed);
 
 void usb_nop_init (usbdev_t *dev);
 void usb_hub_init (usbdev_t *dev);

payloads/libpayload/include/usb/usbmsc.h

@@ -34,13 +34,24 @@ typedef struct {
 	unsigned int numblocks;
 	endpoint_t *bulk_in;
 	endpoint_t *bulk_out;
-	u8 usbdisk_created;
+	u8 quirks		: 7;
+	u8 usbdisk_created	: 1;
 	s8 ready;
 	u8 lun;
 	u8 num_luns;
 	void *data; /* For use by consumers of libpayload. */
 } usbmsc_inst_t;
 
+/* Possible values for quirks field. */
+enum {
+	/* Don't check for LUNs (force assumption that there's only one LUN). */
+	USB_MSC_QUIRK_NO_LUNS	= 1 << 0,
+	/* Never do a BULK_ONLY reset, just continue. This means that the device
+	   cannot recover from phase errors and won't detach automatically for
+	   unrecoverable errors. Do not use unless you have to. */
+	USB_MSC_QUIRK_NO_RESET	= 1 << 1,
+};
+
 /* Possible values for ready field. */
 enum {
 	USB_MSC_DETACHED = -1, /* Disk detached or out to lunch. */
@@ -56,4 +67,8 @@ typedef enum { cbw_direction_data_in = 0x80, cbw_direction_data_out = 0
 int readwrite_blocks_512 (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf);
 int readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf);
 
+/* Force a device to enumerate as MSC, without checking class/protocol types.
+   It must still have a bulk endpoint pair and respond to MSC commands. */
+void usb_msc_force_init (usbdev_t *dev, u32 quirks);
+
 #endif

payloads/libpayload/libc/lib.c

@@ -27,6 +27,7 @@
  * SUCH DAMAGE.
  */
 
+#include <assert.h>
 #include <libpayload.h>
 
 /*
@@ -125,3 +126,54 @@ char *getenv(const char *name)
 {
 	return NULL;
 }
+
+#if !CONFIG(LP_ARCH_MIPS)
+/*
+ * Reads a transfer buffer from 32-bit FIFO registers. fifo_stride is the
+ * distance in bytes between registers (e.g. pass 4 for a normal array of 32-bit
+ * registers or 0 to read everything from the same register). fifo_width is
+ * the amount of bytes read per register (can be 1 through 4).
+ */
+void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
+			int fifo_stride, int fifo_width)
+{
+	u8 *p = buffer;
+	int i, j;
+
+	assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
+	       fifo_stride % sizeof(u32) == 0);
+
+	for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
+		u32 val = read32(fifo);
+		for (j = 0; j < MIN(size - i, fifo_width); j++)
+			*p++ = (u8)(val >> (j * 8));
+	}
+}
+
+/*
+ * Version of buffer_to_fifo32() that can prepend a prefix of up to fifo_width
+ * size to the transfer. This is often useful for protocols where a command word
+ * precedes the actual payload data. The prefix must be packed in the low-order
+ * bytes of the 'prefix' u32 parameter and any high-order bytes exceeding prefsz
+ * must be 0. Note that 'size' counts total bytes written, including 'prefsz'.
+ */
+void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
+			     void *fifo, int fifo_stride, int fifo_width)
+{
+	u8 *p = buffer;
+	int i, j = prefsz;
+
+	assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
+	       fifo_stride % sizeof(u32) == 0 && prefsz <= fifo_width);
+
+	uint32_t val = prefix;
+	for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
+		for (; j < MIN(size - i, fifo_width); j++)
+			val |= *p++ << (j * 8);
+		write32(fifo, val);
+		val = 0;
+		j = 0;
+	}
+
+}
+#endif

payloads/linuxcheck/Makefile

@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile
 # build libpayload and put .config file in $(CURDIR) instead of ../libpayload
 # to avoid pollute the libpayload source directory and possible conflicts
 LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config"
-CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib
+CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib
 ifeq ($(CONFIG_ARCH_X86),y)
 TARGETARCH = i386
 endif

payloads/nvramcui/Makefile

@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile
 # build libpayload and put .config file in $(CURDIR) instead of ../libpayload
 # to avoid pollute the libpayload source directory and possible conflicts
 LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config"
-CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib
+CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib
 
 all: nvramcui.elf
 

src/Kconfig

@@ -484,12 +484,7 @@ source "src/console/Kconfig"
 config HAVE_ACPI_RESUME
 	bool
 	default n
-
+	depends on RELOCATABLE_RAMSTAGE
-config ACPI_HUGE_LOWMEM_BACKUP
-	bool
-	default n
-	help
-	  On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
 
 config RESUME_PATH_SAME_AS_BOOT
 	bool
@@ -991,7 +986,7 @@ config X86EMU_DEBUG_IO
 config X86EMU_DEBUG_TIMINGS
 	bool "Output timing information"
 	default n
-	depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
+	depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
 	help
 	  Print timing information needed by i915tool.
 

src/arch/arm/Kconfig

@@ -1,24 +1,22 @@
 config ARCH_ARM
 	bool
-	default n
 
 config ARCH_BOOTBLOCK_ARM
 	bool
-	default n
 	select ARCH_ARM
 	select C_ENVIRONMENT_BOOTBLOCK
 
 config ARCH_VERSTAGE_ARM
 	bool
-	default n
+	select ARCH_ARM
 
 config ARCH_ROMSTAGE_ARM
 	bool
-	default n
+	select ARCH_ARM
 
 config ARCH_RAMSTAGE_ARM
 	bool
-	default n
+	select ARCH_ARM
 
 source src/arch/arm/armv4/Kconfig
 source src/arch/arm/armv7/Kconfig

src/arch/arm/Makefile.inc

@@ -2,11 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012-2013 The ChromiumOS Authors
-## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
-## Copyright (C) 2009-2010 coresystems GmbH
-## Copyright (C) 2009 Ronald G. Minnich
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

src/arch/arm/armv4/Kconfig

@@ -1,15 +1,15 @@
 config ARCH_BOOTBLOCK_ARMV4
-	def_bool n
+	bool
 	select ARCH_BOOTBLOCK_ARM
 
 config ARCH_VERSTAGE_ARMV4
-	def_bool n
+	bool
 	select ARCH_VERSTAGE_ARM
 
 config ARCH_ROMSTAGE_ARMV4
-	def_bool n
+	bool
 	select ARCH_ROMSTAGE_ARM
 
 config ARCH_RAMSTAGE_ARMV4
-	def_bool n
+	bool
 	select ARCH_RAMSTAGE_ARM

src/arch/arm/armv4/Makefile.inc

@@ -2,8 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2013 The ChromiumOS Authors
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

src/arch/arm/armv4/bootblock.S

@@ -1,17 +1,5 @@
 /*
- * Early initialization code for ARM architecture.
+ * This file is part of the coreboot project.
- *
- * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
- * U-Boot, which itself got the file from armboot.
- *
- * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003	Kshitij <kshitij@ti.com>
- * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
- * Copyright (c) 2013   The Chromium OS Authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,6 +10,11 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Early initialization code for ARM architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
  */
 
 #include <arch/asm.h>

src/arch/arm/armv7/Kconfig

@@ -1,37 +1,39 @@
 config ARCH_BOOTBLOCK_ARMV7
-	def_bool n
+	bool
 	select ARCH_BOOTBLOCK_ARM
 
 config ARCH_VERSTAGE_ARMV7
-	def_bool n
+	bool
 	select ARCH_VERSTAGE_ARM
 
 config ARCH_ROMSTAGE_ARMV7
-	def_bool n
+	bool
 	select ARCH_ROMSTAGE_ARM
 
 config ARCH_RAMSTAGE_ARMV7
-	def_bool n
+	bool
 	select ARCH_RAMSTAGE_ARM
+
 config ARCH_BOOTBLOCK_ARMV7_M
-	def_bool n
+	bool
 	select ARCH_BOOTBLOCK_ARM
+
 config ARCH_VERSTAGE_ARMV7_M
-	def_bool n
+	bool
 	select ARCH_VERSTAGE_ARM
 
 config ARCH_BOOTBLOCK_ARMV7_R
-	def_bool n
+	bool
 	select ARCH_BOOTBLOCK_ARM
 
 config ARCH_VERSTAGE_ARMV7_R
-	def_bool n
+	bool
 	select ARCH_VERSTAGE_ARM
 
 config ARCH_ROMSTAGE_ARMV7_R
-	def_bool n
+	bool
 	select ARCH_ROMSTAGE_ARM
 
 config ARCH_RAMSTAGE_ARMV7_R
-	def_bool n
+	bool
 	select ARCH_RAMSTAGE_ARM

src/arch/arm/armv7/Makefile.inc

@@ -2,8 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2013 The ChromiumOS Authors
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

src/arch/arm/armv7/bootblock.S

@@ -1,17 +1,5 @@
 /*
- * Early initialization code for ARMv7 architecture.
+ * This file is part of the coreboot project.
- *
- * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
- * U-Boot, which itself got the file from armboot.
- *
- * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
- * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003	Kshitij <kshitij@ti.com>
- * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
- * Copyright (c) 2013   The Chromium OS Authors
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -22,6 +10,11 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Early initialization code for ARMv7 architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
  */
 
 #include <arch/asm.h>

src/arch/arm/armv7/cpu.S

@@ -1,7 +1,5 @@
 /*
- * Optimized assembly for low-level CPU operations on ARMv7 processors.
+ * This file is part of the coreboot project.
- *
- * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
  *
  * Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
  * Copyright (c) 2014 Google Inc.
@@ -28,6 +26,10 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
+ * Optimized assembly for low-level CPU operations on ARMv7 processors.
+ *
+ * Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
  */
 
 #include <arch/asm.h>

src/arch/arm/armv7/exception.c

@@ -1,5 +1,5 @@
 /*
- * This file is part of the libpayload project.
+ * This file is part of the coreboot project.
  *
  * Copyright 2013 Google Inc.
  *

src/arch/arm/armv7/exception_asm.S

@@ -1,5 +1,5 @@
 /*
- * This file is part of the libpayload project.
+ * This file is part of the coreboot project.
  *
  * Copyright 2013 Google Inc.
  *

src/arch/arm/armv7/exception_mr.c

@@ -1,5 +1,5 @@
 /*
- * This file is part of the libpayload project.
+ * This file is part of the coreboot project.
  *
  * Copyright 2013 Google Inc.
  *

src/arch/arm/armv7/thread.c

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 Google, Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/asmlib.h

@@ -1,9 +1,5 @@
 /*
- *  arch/arm/asmlib.h
+ * This file is part of the coreboot project.
- *
- *  Adapted from Linux arch/arm/include/assembler.h
- *
- *  Copyright (C) 1996-2000 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,6 +13,8 @@
  *  This file contains arm architecture specific defines
  *  for the different processors.
  *
+ *  Adapted from Linux arch/arm/include/assembler.h
+ *
  *  Do not include any C declarations in this file - it is included by
  *  assembler source.
  */

src/arch/arm/boot.c

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/div0.c

@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2002
+ * This file is part of the coreboot project.
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

src/arch/arm/eabi_compat.c

@@ -1,7 +1,5 @@
 /*
- * Utility functions needed for (some) EABI conformant tool chains.
+ * This file is part of the coreboot project.
- *
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
  *
  * This program is Free Software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -12,6 +10,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Utility functions needed for (some) EABI conformant tool chains.
  */
 
 #include <stdint.h>

src/arch/arm/include/arch/asm.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/cbconfig.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2016 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/clock.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/early_variables.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -20,7 +18,9 @@
 
 static inline void *car_get_var_ptr(void *var) { return var; }
 #define car_get_var(var) (var)
-#define car_sync_var(var) (var)
 #define car_set_var(var, val) do { (var) = (val); } while (0)
 
+#define car_get_ptr car_get_var
+#define car_set_ptr car_set_var
+
 #endif

src/arch/arm/include/arch/header.ld

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/memlayout.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2014 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/pci_ops.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2013 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/arch/stages.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2013 The ChromiumOS Authors
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/armv4/arch/cpu.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2012 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/include/armv4/arch/mmio.h

@@ -1,9 +1,5 @@
 /*
- * Originally imported from linux/include/asm-arm/io.h. This file has changed
+ * This file is part of the coreboot project.
- * substantially since then.
- *
- *  Copyright 2013 Google Inc.
- *  Copyright (C) 1996-2000 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,16 +10,8 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * Modifications:
+ * Originally imported from linux/include/asm-arm/io.h. This file has changed
- *  08-Apr-2013	G	Replaced several macros with inlines for type safety.
+ * substantially since then.
- *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
- *			constant addresses and variable addresses.
- *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
- *			specific IO header files.
- *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
- *  04-Apr-1999	PJB	Added check_signature.
- *  12-Dec-1999	RMK	More cleanups
- *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
  */
 
 #ifndef __ARCH_MMIO_H__

src/arch/arm/include/armv7.h

@@ -1,7 +1,5 @@
 /*
- * (C) Copyright 2010
+ * This file is part of the coreboot project.
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

src/arch/arm/include/armv7/arch/cpu.h

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2012 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
@@ -17,12 +15,10 @@
 #define __ARCH_CPU_H__
 
 #include <stdint.h>
+#include <device/device.h>
 
 #define asmlinkage
 
-#if !defined(__PRE_RAM__)
-#include <device/device.h>
-
 struct cpu_driver {
 	struct device_operations *ops;
 	const struct cpu_device_id *id_table;
@@ -34,8 +30,6 @@ struct cpuinfo_arm {
 	uint8_t    arm_model;
 };
 
-#endif
-
 /* Primitives for CPU and MP cores. */
 
 /* read Main Id register (MIDR) */

src/arch/arm/include/armv7/arch/exception.h

@@ -1,5 +1,5 @@
 /*
- * This file is part of the libpayload project.
+ * This file is part of the coreboot project.
  *
  * Copyright 2013 Google Inc.
  *

src/arch/arm/include/armv7/arch/mmio.h

@@ -1,9 +1,5 @@
 /*
- * Originally imported from linux/include/asm-arm/io.h. This file has changed
+ * This file is part of the coreboot project.
- * substantially since then.
- *
- *  Copyright 2013 Google Inc.
- *  Copyright (C) 1996-2000 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,16 +10,8 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * Modifications:
+ * Originally imported from linux/include/asm-arm/io.h. This file has changed
- *  08-Apr-2013	G	Replaced several macros with inlines for type safety.
+ * substantially since then.
- *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
- *			constant addresses and variable addresses.
- *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
- *			specific IO header files.
- *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
- *  04-Apr-1999	PJB	Added check_signature.
- *  12-Dec-1999	RMK	More cleanups
- *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
  */
 
 #ifndef __ARCH_MMIO_H__

src/arch/arm/include/clocks.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 The Chromium OS Authors.
+ * This file is part of the coreboot project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

src/arch/arm/libgcc/Makefile.inc

@@ -2,8 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2013 The ChromiumOS Authors
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

src/arch/arm/libgcc/ashldi3.S

@@ -1,5 +1,5 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+/*
-   Free Software Foundation, Inc.
+This file is part of the coreboot project.
 
 This file is free software; you can redistribute it and/or modify it
 under the terms of the GNU General Public License as published by the

src/arch/arm/libgcc/lib1funcs.S

@@ -1,12 +1,5 @@
 /*
- * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+This file is part of the coreboot project.
- *
- * Author: Nicolas Pitre <nico@fluxnic.net>
- *   - contributed to gcc-3.4 on Sep 30, 2003
- *   - adapted for the Linux kernel on Oct 2, 2003
- */
-
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify it
 under the terms of the GNU General Public License as published by the
@@ -28,6 +21,10 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 General Public License for more details.
 */
 
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ */
+
 
 #if defined __GNUC__
 

src/arch/arm/libgcc/lshrdi3.S

@@ -1,5 +1,5 @@
-/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005
+/*
-   Free Software Foundation, Inc.
+This file is part of the coreboot project.
 
 This file is free software; you can redistribute it and/or modify it
 under the terms of the GNU General Public License as published by the

src/arch/arm/libgcc/muldi3.S

@@ -1,9 +1,5 @@
 /*
- *  linux/arch/arm/lib/muldi3.S
+ * This file is part of the coreboot project.
- *
- *  Author:     Nicolas Pitre
- *  Created:    Oct 19, 2005
- *  Copyright:  Monta Vista Software, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +9,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Based on linux/arch/arm/lib/muldi3.S
  */
 
 #if defined __GNUC__

src/arch/arm/libgcc/ucmpdi2.S

@@ -1,9 +1,5 @@
 /*
- *  linux/arch/arm/lib/ucmpdi2.S
+ * This file is part of the coreboot project.
- *
- *  Author:	Nicolas Pitre
- *  Created:	Oct 19, 2005
- *  Copyright:	Monta Vista Software, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +9,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Based on linux/arch/arm/lib/ucmpdi2.S
  */
 
 #if defined __GNUC__

src/arch/arm/libgcc/uldivmod.S

@@ -1,4 +1,6 @@
 /*
+ * This file is part of the coreboot project.
+ *
  * Copyright 2010, Google Inc.
  * All rights reserved.
  *

src/arch/arm/memcpy.S

@@ -1,9 +1,5 @@
 /*
- *  linux/arch/arm/lib/memcpy.S
+ * This file is part of the coreboot project.
- *
- *  Author:	Nicolas Pitre
- *  Created:	Sep 28, 2005
- *  Copyright:	MontaVista Software, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +9,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Based on linux/arch/arm/lib/memcpy.S
  */
 
 #include <arch/asm.h>

src/arch/arm/memmove.S

@@ -1,9 +1,5 @@
 /*
- *  linux/arch/arm/lib/memmove.S
+ * This file is part of the coreboot project.
- *
- *  Author:	Nicolas Pitre
- *  Created:	Sep 28, 2005
- *  Copyright:	(C) MontaVista Software Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,6 +9,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Based on linux/arch/arm/lib/memmove.S
  */
 
 #include <arch/asm.h>

src/arch/arm/memset.S

@@ -1,7 +1,5 @@
 /*
- *  linux/arch/arm/lib/memset.S
+ * This file is part of the coreboot project.
- *
- *  Copyright (C) 1995-2000 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,6 +10,8 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
+ * Based on linux/arch/arm/lib/memset.S
+ *
  * ASM optimised string functions
  */
 

src/arch/arm/stages.c

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2012 Google Inc.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm/tables.c

@@ -1,10 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2003 Eric Biederman
- * Copyright (C) 2005 Steve Magnani
- * Copyright (C) 2008-2009 coresystems GmbH
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.

src/arch/arm64/Kconfig

@@ -1,27 +1,27 @@
 config ARCH_ARM64
 	bool
-	default n
 
 config ARCH_BOOTBLOCK_ARM64
 	bool
-	default n
 	select ARCH_ARM64
 	select C_ENVIRONMENT_BOOTBLOCK
 
 config ARCH_VERSTAGE_ARM64
 	bool
-	default n
+	select ARCH_ARM64
 
 config ARCH_ROMSTAGE_ARM64
 	bool
-	default n
+	select ARCH_ARM64
 
 config ARCH_RAMSTAGE_ARM64
 	bool
-	default n
+	select ARCH_ARM64
 
 source src/arch/arm64/armv8/Kconfig
 
+if ARCH_ARM64
+
 config ARM64_USE_ARCH_TIMER
 	bool
 	default n
@@ -58,3 +58,5 @@ config ARM64_A53_ERRATUM_843419
 	  incorrect address calculations in rare cases. This option enables a
 	  linker workaround to avoid those cases if your toolchain supports it.
 	  Should be selected automatically by SoCs that are affected.
+
+endif # if ARCH_ARM64

src/arch/arm64/Makefile.inc

@@ -2,12 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2014 Google Inc.
-## Copyright (C) 2012-2013 The ChromiumOS Authors
-## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
-## Copyright (C) 2009-2010 coresystems GmbH
-## Copyright (C) 2009 Ronald G. Minnich
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.
@@ -107,6 +101,7 @@ romstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 romstage-y += memset.S
 romstage-y += memcpy.S
 romstage-y += memmove.S
+romstage-y += ramdetect.c
 romstage-y += romstage.c
 romstage-y += transition.c transition_asm.S
 
@@ -131,11 +126,12 @@ ramstage-y += div0.c
 ramstage-y += eabi_compat.c
 ramstage-y += boot.c
 ramstage-y += tables.c
+ramstage-y += ramdetect.c
 ramstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 ramstage-y += memset.S
 ramstage-y += memcpy.S
 ramstage-y += memmove.S
-ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c
+ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c
 ramstage-y += transition.c transition_asm.S
 ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c
 

src/arch/arm64/arch_timer.c

@@ -1,8 +1,6 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.

src/arch/arm64/arm_tf.c

@@ -1,92 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/lib_helpers.h>
-#include <arch/mmu.h>
-#include <arch/transition.h>
-#include <arm_tf.h>
-#include <bootmem.h>
-#include <cbfs.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-/*
- * TODO: Many of these structures are currently unused. Better not fill them out
- * to make future changes fail fast, rather than try to come up with content
- * that might turn out to not make sense. Implement later as required.
- *
-static image_info_t bl31_image_info;
-static image_info_t bl32_image_info;
-static image_info_t bl33_image_info;
- */
-static entry_point_info_t bl32_ep_info;
-static entry_point_info_t bl33_ep_info;
-static bl31_params_t bl31_params;
-
-void __weak *soc_get_bl31_plat_params(bl31_params_t *params)
-{
-	/* Default weak implementation. */
-	return NULL;
-}
-
-void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
-{
-	struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31");
-	void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL;
-
-	if (prog_locate(&bl31))
-		die("BL31 not found");
-
-	if (!selfload_check(&bl31, BM_MEM_BL31))
-		die("BL31 load failed");
-	bl31_entry = prog_entry(&bl31);
-
-	SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
-
-	if (CONFIG(ARM64_USE_SECURE_OS)) {
-		struct prog bl32 = PROG_INIT(PROG_BL32,
-					     CONFIG_CBFS_PREFIX"/secure_os");
-
-		if (prog_locate(&bl32))
-			die("BL32 not found");
-
-		if (cbfs_prog_stage_load(&bl32))
-			die("BL32 load failed");
-
-		SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1,
-			       PARAM_EP_SECURE);
-		bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32);
-		bl32_ep_info.spsr = SPSR_EXCEPTION_MASK |
-				get_eret_el(EL1, SPSR_USE_L);
-		bl31_params.bl32_ep_info = &bl32_ep_info;
-	}
-
-	bl31_params.bl33_ep_info = &bl33_ep_info;
-
-	SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE);
-	bl33_ep_info.pc = payload_entry;
-	bl33_ep_info.spsr = payload_spsr;
-	bl33_ep_info.args.arg0 = payload_arg0;
-
-	/* May update bl31_params if necessary. */
-	void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params);
-
-	/* MMU disable will flush cache, so passed params land in memory. */
-	raw_write_daif(SPSR_EXCEPTION_MASK);
-	mmu_disable();
-	bl31_entry(&bl31_params, bl31_plat_params);
-	die("BL31 returned!");
-}

src/arch/arm64/armv8/Kconfig

@@ -1,17 +1,17 @@
 config ARCH_BOOTBLOCK_ARMV8_64
-	def_bool n
+	bool
 	select ARCH_BOOTBLOCK_ARM64
 
 config ARCH_VERSTAGE_ARMV8_64
-	def_bool n
+	bool
 	select ARCH_VERSTAGE_ARM64
 
 config ARCH_ROMSTAGE_ARMV8_64
-	def_bool n
+	bool
 	select ARCH_ROMSTAGE_ARM64
 
 config ARCH_RAMSTAGE_ARMV8_64
-	def_bool n
+	bool
 	select ARCH_RAMSTAGE_ARM64
 
 config ARCH_ARMV8_EXTENSION

src/arch/arm64/armv8/Makefile.inc

@@ -2,8 +2,6 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2014 The ChromiumOS Authors
-##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; version 2 of the License.

src/arch/arm64/armv8/bootblock.S

@@ -1,7 +1,5 @@
 /*
- * Early initialization code for aarch64 (a.k.a. armv8)
+ * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -12,6 +10,8 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
+ *
+ * Early initialization code for aarch64 (a.k.a. armv8)
  */
 
 #include <arch/asm.h>