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soc/intel/tigerlake: Add values for GMA registers

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Change-Id: Id5dbf50c501e5fdd64a194d064198c776ab3d897
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2021-09-21 23:23:14 -06:00
committed by Jeremy Soller
parent 32f3311f3e
commit 5807b15bc2
1 changed files with 12 additions and 0 deletions
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src/soc/intel/tigerlake/Kconfig
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@@ -258,6 +258,18 @@ config EARLY_TCSS_DISPLAY
help help
Enable displays to be detected over Type-C ports during boot. Enable displays to be detected over Type-C ports during boot.
config INTEL_GMA_BCLV_OFFSET
default 0xc8258
config INTEL_GMA_BCLV_WIDTH
default 32
config INTEL_GMA_BCLM_OFFSET
default 0xc8254
config INTEL_GMA_BCLM_WIDTH
default 32
config DISABLE_ME config DISABLE_ME
bool "Disable the IME by setting the HAP bit at run-time" bool "Disable the IME by setting the HAP bit at run-time"
# XXX: Prevents CPU from reaching C10 # XXX: Prevents CPU from reaching C10