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Update galp5 power limits

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Change-Id: Ic9b22570cc2e61b5489f7bbdb58e7920a4507b7f
This commit is contained in:
Jeremy Soller
2020-10-27 08:36:48 -06:00
parent 467ae4536d
commit 581081092e
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/system76/galp5/devicetree.cb
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@@ -23,13 +23,13 @@ chip soc/intel/tigerlake
# Power limits # Power limits
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 15, .tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 60, .tdp_pl2_override = 60,
}" }"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 15, .tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 60, .tdp_pl2_override = 60,
}" }"
@@ -72,7 +72,7 @@ chip soc/intel/tigerlake
# System Agent dynamic frequency support # System Agent dynamic frequency support
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
#TODO: TCSS USB3 # TCSS USB3
register "TcssXhciEn" = "1" register "TcssXhciEn" = "1"
# FSP Silicon (soc/intel/tigerlake/fsp_params.c) # FSP Silicon (soc/intel/tigerlake/fsp_params.c)
@@ -177,7 +177,7 @@ chip soc/intel/tigerlake
register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gfx" = "GMA_STATIC_DISPLAYS(0)"
# PMC (soc/intel/tigerlake/pmc.c) # PMC (soc/intel/tigerlake/pmc.c)
# TODO: Disable deep Sx states # Disable deep Sx states
register "deep_s3_enable_ac" = "0" register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0" register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0" register "deep_s5_enable_ac" = "0"