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intel/cannonlake_rvp: Enable Audio DSP

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Enable Audio DSP by default on cannonlake rvp platform.

TEST=Boot up into OS and check Audio driver debug print.

Change-Id: I6892c6d349019550c967ef30b84d385f396fc388
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao
2017-10-04 18:19:14 -07:00
committed by Aaron Durbin
parent 0b21ad9e80
commit 584af87483
2 changed files with 6 additions and 0 deletions
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3
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -33,6 +33,9 @@ chip soc/intel/cannonlake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"

3
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -33,6 +33,9 @@ chip soc/intel/cannonlake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"