mb/ocp/deltalake: Override DDR frequency limit via VPD variable
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit. Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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@@ -13,6 +13,35 @@
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#include "ipmi.h"
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#include "vpd.h"
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/* Convert the vpd integer to the DDR frenquency limit enum */
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static enum ddr_freq_limit ddr_freq_limit(int num)
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{
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switch (num) {
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case 0:
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return DDR_AUTO;
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case 1:
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return DDR_1333;
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case 2:
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return DDR_1600;
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case 3:
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return DDR_1866;
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case 4:
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return DDR_2133;
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case 5:
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return DDR_2400;
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case 6:
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return DDR_2666;
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case 7:
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return DDR_2933;
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case 8:
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return DDR_3200;
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default:
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printk(BIOS_WARNING, "Invalid DdrFreqLimit value from VPD: "
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"%d\n", num);
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return DDR_AUTO;
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};
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}
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/*
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* Search from VPD_RW first then VPD_RO for UPD config variables,
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* overwrites them from VPD if it's found.
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@@ -77,6 +106,17 @@ static void mainboard_config_upd(FSPM_UPD *mupd)
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printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val_int);
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mupd->FspmConfig.UnusedUpdSpace0[0] = (uint8_t)val_int;
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}
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/* Select DDR Frequency Limit */
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if (vpd_get_int(FSP_DIMM_FREQ, VPD_RW_THEN_RO, (int *const) &val_int)) {
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printk(BIOS_INFO, "Setting DdrFreqLimit %d from VPD\n", val_int);
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mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(val_int);
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} else {
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printk(BIOS_WARNING, "Not able to get VPD %s, default set "
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"DdrFreqLimit to %d\n", FSP_DIMM_FREQ,
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FSP_DIMM_FREQ_DEFAULT);
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mupd->FspmConfig.DdrFreqLimit = ddr_freq_limit(FSP_DIMM_FREQ_DEFAULT);
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}
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}
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/* Update bifurcation settings according to different Configs */
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@@ -41,4 +41,9 @@
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#define COREBOOT_UART_IO "coreboot_uart_io"
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#define COREBOOT_UART_IO_DEFAULT 1
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/* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133,
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* 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */
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#define FSP_DIMM_FREQ "fsp_dimm_freq"
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#define FSP_DIMM_FREQ_DEFAULT 0
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#endif
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@@ -31,6 +31,21 @@ typedef enum {
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PcieGen3
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} pcie_link_speed;
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/**
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enum for DDR Frequency Limit
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**/
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enum ddr_freq_limit {
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DDR_AUTO = 0x0,
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DDR_1333 = 0x5,
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DDR_1600 = 0x7,
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DDR_1866 = 0x9,
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DDR_2133 = 0xb,
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DDR_2400 = 0xd,
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DDR_2666 = 0xf,
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DDR_2933 = 0x11,
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DDR_3200 = 0x13
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};
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struct soc_intel_xeon_sp_cpx_config {
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/* Common struct containing soc config data required by common code */
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struct soc_intel_common_config common_soc_config;
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